X-SAT: An Efficient Circuit-Based SAT Solver

In modern digital circuit design, verifying the equivalence of arithmetic circuits is a significant and challenging task. This paper introduces a new circuit solver based on the Conflict-Driven Clause Learning (CDCL) algorithm, which integrates structural elimination techniques to reduce the number...

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Vydané v:	2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori:	Qian, Yuhang, Chen, Zhihan, Zhang, Xindi, Cai, Shaowei
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 22.06.2025
Predmet:	Arithmetic Benchmark testing Boolean satisfiability Circuit synthesis Circuit-based SAT Circuits Design automation Digital circuits EDA Equivalence checking Logic gates Performance gain Robustness
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