Supporting Register-based Addressing Modes for in-DRAM PIM ISAs

Processing-in-Memory architecture presents a promising solution to alleviate the data movement bottleneck that arises from transferring data between memory and compute units in traditional processor-centric systems, particularly for DNN applications. However, this architecture introduces two inheren...

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Bibliographic Details

Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors:	Kim, Seok Young, Choi, Byung Ho, Kang, Seokwon, Park, Yongjun, Kim, Seon Wook
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Code Offloading Codes Computer architecture Data transfer Design automation Look-up Table Performance evaluation PIM ISA Power demand Processing-in-DRAM Register-based Addressing Mode Registers Runtime Table lookup
Online Access:	Get full text
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