Supporting Register-based Addressing Modes for in-DRAM PIM ISAs

Processing-in-Memory architecture presents a promising solution to alleviate the data movement bottleneck that arises from transferring data between memory and compute units in traditional processor-centric systems, particularly for DNN applications. However, this architecture introduces two inheren...

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Bibliographic Details
Published in:2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 6
Main Authors: Kim, Seok Young, Choi, Byung Ho, Kang, Seokwon, Park, Yongjun, Kim, Seon Wook
Format: Conference Proceeding
Language:English
Published: IEEE 22.06.2025
Subjects:
Code Offloading
Codes
Computer architecture
Data transfer
Design automation
Look-up Table
Performance evaluation
PIM ISA
Power demand
Processing-in-DRAM
Register-based Addressing Mode
Registers
Runtime
Table lookup
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Summary:Processing-in-Memory architecture presents a promising solution to alleviate the data movement bottleneck that arises from transferring data between memory and compute units in traditional processor-centric systems, particularly for DNN applications. However, this architecture introduces two inherent overheads: PIM code offloading and data transferring between CPU and memory. To address these issues, we propose two register-based addressing modes, indexed and base-offset addressing, for DMA descriptor-based in-DRAM PIM ISAs. Our full-system performance evaluation demonstrates that the approach significantly reduces the overheads, resulting in up to 1.94x speedup compared to the baseline PIM, additionally only with 4.65 \% area and 8.61 \% power consumption.
DOI:10.1109/DAC63849.2025.11132430