Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design

SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these...

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Bibliographic Details

Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors:	Zhou, Jie, Ji, Youshu, Wang, Ning, Hu, Yuchen, Jiao, Xinyao, Yao, Bingkun, Fang, Xinwei, Zhao, Shuai, Guan, Nan, Jiang, Zhe
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Data augmentation Design automation Hardware Large language models Measurement Register transfer level Reliability Timing Training Training data
Online Access:	Get full text
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