Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design

SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these...

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Vydáno v:2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autoři: Zhou, Jie, Ji, Youshu, Wang, Ning, Hu, Yuchen, Jiao, Xinyao, Yao, Bingkun, Fang, Xinwei, Zhao, Shuai, Guan, Nan, Jiang, Zhe
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 22.06.2025
Témata:
Data augmentation
Design automation
Hardware
Large language models
Measurement
Register transfer level
Reliability
Timing
Training
Training data
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Abstract SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these failures, i.e., identifying and fixing the issues causing the deviation, requires analysing complex logical and timing relationships between multiple signals. This process heavily relies on human expertise, and there is currently no automatic tool available to assist with it. Here, we present AssertSolver, an opensource Large Language Model (LLM) specifically designed for solving assertion failures. By leveraging synthetic training data and learning from error responses to challenging cases, AssertSolver achieves a bug-fixing pass@1 metric of 88.54% on our testbench, significantly outperforming OpenAI's o1-preview by up to \mathbf{1 1. 9 7 \%}. We release our model and testbench for public access to encourage further research: https://github.com/SEU-ACAL/reproduce-AssertSolver-DAC-25.
AbstractList SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours. During simulation, assertion failures occur when the design's behaviour deviates from expectations. Solving these failures, i.e., identifying and fixing the issues causing the deviation, requires analysing complex logical and timing relationships between multiple signals. This process heavily relies on human expertise, and there is currently no automatic tool available to assist with it. Here, we present AssertSolver, an opensource Large Language Model (LLM) specifically designed for solving assertion failures. By leveraging synthetic training data and learning from error responses to challenging cases, AssertSolver achieves a bug-fixing pass@1 metric of 88.54% on our testbench, significantly outperforming OpenAI's o1-preview by up to \mathbf{1 1. 9 7 \%}. We release our model and testbench for public access to encourage further research: https://github.com/SEU-ACAL/reproduce-AssertSolver-DAC-25.
Author Zhou, Jie
Jiang, Zhe
Hu, Yuchen
Jiao, Xinyao
Fang, Xinwei
Zhao, Shuai
Wang, Ning
Yao, Bingkun
Ji, Youshu
Guan, Nan
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  surname: Jiang
  fullname: Jiang, Zhe
  email: zhejiang.uk@gmail.com
  organization: Southeast University,School of Integrated Circuits,China
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Snippet SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect...
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SubjectTerms Data augmentation
Design automation
Hardware
Large language models
Measurement
Register transfer level
Reliability
Timing
Training
Training data
Title Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
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