GLiTCH: GLiTCH induced Transitions for Secure Crypto-Hardware

Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time cont...

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Vydané v:	2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori:	Menon, C. Rohin, Balasubramanian, Jayanth, Akshay Kumar, E, Valiveti, Annapurna, Rebeiro, Chester, Viraraghavan, Janakiraman
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 22.06.2025
Predmet:	Ciphers Design automation Entropy gate-resizing geometric programming Glitches Logic gates Programming Security Side-channel attacks Timing
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