GLiTCH: GLiTCH induced Transitions for Secure Crypto-Hardware

Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time cont...

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Veröffentlicht in:2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 7
Hauptverfasser: Menon, C. Rohin, Balasubramanian, Jayanth, Akshay Kumar, E, Valiveti, Annapurna, Rebeiro, Chester, Viraraghavan, Janakiraman
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 22.06.2025
Schlagworte:
Ciphers
Design automation
Entropy
gate-resizing
geometric programming
Glitches
Logic gates
Programming
Security
Side-channel attacks
Timing
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Abstract Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time control, which is cast as a Geometric Programming formulation. We develop a framework, GLiTCH, for glitch manipulation that is guided by functional and timing simulations. The framework is evaluated on popular cipher designs like AES, CLEFIA, and SM4. Our findings illustrate up to 52.82% improvement in the Guessing Entropy for a 38.74% area overhead on average across the evaluated ciphers.
AbstractList Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time control, which is cast as a Geometric Programming formulation. We develop a framework, GLiTCH, for glitch manipulation that is guided by functional and timing simulations. The framework is evaluated on popular cipher designs like AES, CLEFIA, and SM4. Our findings illustrate up to 52.82% improvement in the Guessing Entropy for a 38.74% area overhead on average across the evaluated ciphers.
Author Menon, C. Rohin
Valiveti, Annapurna
Viraraghavan, Janakiraman
Rebeiro, Chester
Balasubramanian, Jayanth
Akshay Kumar, E
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  givenname: Jayanth
  surname: Balasubramanian
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  surname: Akshay Kumar
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  organization: Indian Institute of Technology Madras,India
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  surname: Valiveti
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  organization: Indian Institute of Technology Madras,India
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  organization: Indian Institute of Technology Madras,India
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  givenname: Janakiraman
  surname: Viraraghavan
  fullname: Viraraghavan, Janakiraman
  organization: Indian Institute of Technology Madras,India
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Snippet Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition...
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SubjectTerms Ciphers
Design automation
Entropy
gate-resizing
geometric programming
Glitches
Logic gates
Programming
Security
Side-channel attacks
Timing
Title GLiTCH: GLiTCH induced Transitions for Secure Crypto-Hardware
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