GLiTCH: GLiTCH induced Transitions for Secure Crypto-Hardware

Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time cont...

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Vydané v:2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori: Menon, C. Rohin, Balasubramanian, Jayanth, Akshay Kumar, E, Valiveti, Annapurna, Rebeiro, Chester, Viraraghavan, Janakiraman
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 22.06.2025
Predmet:
Ciphers
Design automation
Entropy
gate-resizing
geometric programming
Glitches
Logic gates
Programming
Security
Side-channel attacks
Timing
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Shrnutí:Conventionally, glitch reduction is well-studied in digital design to improve power, efficiency, and security. In contrast, this paper combines the addition and removal of glitches to minimize the power side-channel leakage. Glitch Manipulation is achieved through gate sizing-based arrival time control, which is cast as a Geometric Programming formulation. We develop a framework, GLiTCH, for glitch manipulation that is guided by functional and timing simulations. The framework is evaluated on popular cipher designs like AES, CLEFIA, and SM4. Our findings illustrate up to 52.82% improvement in the Guessing Entropy for a 38.74% area overhead on average across the evaluated ciphers.
DOI:10.1109/DAC63849.2025.11133057