Clearance-Constrained PCB Global Placement with Heterogeneous Components
The complexity of design rules and intense time-to-market demands have made auto-placement tools essential for advanced printed circuit board (PCB) designs. This paper presents a novel PCB placement framework to handle pad-to-pad clearance constraints and heterogeneous components to address these ch...
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| Vydáno v: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7 |
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22.06.2025
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| Abstract | The complexity of design rules and intense time-to-market demands have made auto-placement tools essential for advanced printed circuit board (PCB) designs. This paper presents a novel PCB placement framework to handle pad-to-pad clearance constraints and heterogeneous components to address these challenges. Unlike existing academic placers, our framework focuses on the following key features: a wire-area model to account for various routing resource needs between power and signal nets, a pad-to-pad clearance model to minimize spacing violations, and a two-sided, pad-type-aware density model to reduce component and pad overlap. We further develop a quadratic programming-based legalizer to resolve constraint violations among components of varying shapes. Experimental results show the effectiveness and efficiency of our framework, surpassing two state-of-theart academic placers in post-routing quality on both academic and industrial benchmarks. |
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| AbstractList | The complexity of design rules and intense time-to-market demands have made auto-placement tools essential for advanced printed circuit board (PCB) designs. This paper presents a novel PCB placement framework to handle pad-to-pad clearance constraints and heterogeneous components to address these challenges. Unlike existing academic placers, our framework focuses on the following key features: a wire-area model to account for various routing resource needs between power and signal nets, a pad-to-pad clearance model to minimize spacing violations, and a two-sided, pad-type-aware density model to reduce component and pad overlap. We further develop a quadratic programming-based legalizer to resolve constraint violations among components of varying shapes. Experimental results show the effectiveness and efficiency of our framework, surpassing two state-of-theart academic placers in post-routing quality on both academic and industrial benchmarks. |
| Author | Tsai, Chung-Ting Huang, Wei-Kai Ou, Chiao-Yu Chang, Yao-Wen Chen, Yan-Jen |
| Author_xml | – sequence: 1 givenname: Yan-Jen surname: Chen fullname: Chen, Yan-Jen email: yjchen@eda.ee.ntu.edu.tw organization: Graduate Institute of Electronics Engineering National Taiwan University,Taipei,Taiwan,106319 – sequence: 2 givenname: Wei-Kai surname: Huang fullname: Huang, Wei-Kai email: wkhuang@eda.ee.ntu.edu.tw organization: Graduate Institute of Electronics Engineering National Taiwan University,Taipei,Taiwan,106319 – sequence: 3 givenname: Chung-Ting surname: Tsai fullname: Tsai, Chung-Ting email: b09901020@ntu.edu.tw organization: National Taiwan University,Department of Electrical Engineering,Taipei,Taiwan,106319 – sequence: 4 givenname: Chiao-Yu surname: Ou fullname: Ou, Chiao-Yu email: cyou@eda.ee.ntu.edu.tw organization: Graduate Institute of Electronics Engineering National Taiwan University,Taipei,Taiwan,106319 – sequence: 5 givenname: Yao-Wen surname: Chang fullname: Chang, Yao-Wen email: ywchang@ntu.edu.tw organization: Graduate Institute of Electronics Engineering National Taiwan University,Taipei,Taiwan,106319 |
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| SubjectTerms | Benchmark testing Complexity theory Design automation Integrated circuit modeling Printed circuits Routing Shape Signal resolution |
| Title | Clearance-Constrained PCB Global Placement with Heterogeneous Components |
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