SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM

Processing in Memory (PIM) architectures enhance memory bandwidth by utilizing bank-level parallelism, typically implemented with a SIMD structure where all banks operate simultaneously under a single command. However, this synchronous approach requires the activation of all banks before computation...

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Bibliographic Details

Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors:	Yoon, Byungkuk, Han, Sanghyeok, Park, Gyeonghwan, Kim, Jae-Joon
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Design automation Limiting Memory architecture Performance gain Periodic structures Random access memory Reservoirs Single instruction multiple data Synchronization Throughput
Online Access:	Get full text
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