BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation
Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically, reasoning datapath and adder tree in bit-blasted Boolean networks is particularly crucial for verification and synthesis, and challenging. Convent...
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| Published in: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7 |
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| Format: | Conference Proceeding |
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IEEE
22.06.2025
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| Abstract | Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically, reasoning datapath and adder tree in bit-blasted Boolean networks is particularly crucial for verification and synthesis, and challenging. Conventional approaches either fail to accurately (exactly) identify the function blocks of the designs in gate-level netlist with structural hashing and symbolic propagation, or their reasoning performance is highly sensitive to structure modifications caused by technology mapping or logic optimization. This paper introduces BoolE, an exact symbolic reasoning framework for Boolean netlists using equality saturation. BoolE optimizes scalability and performance by integrating domain-specific Boolean ruleset for term rewriting. We incorporate a novel extraction algorithm into BoolE to enhance its structural insight and computational efficiency, which adeptly identifies and captures multi-input, multi-output high-level structures (e.g., full adder) in the reconstructed e-graph. Our experiments show that BoolE surpasses state-of-the-art symbolic reasoning baselines, including the conventional functional approach (ABC) and machine learning-based method (Gamora). Specifically, we evaluated its performance on various multiplier architecture with different configurations. Our results show that BoolE identifies 3.53 \times and 3.01 \times more exact full adders than ABC in carry-save array and Booth-encoded multipliers, respectively. Additionally, we integrated BoolE into multiplier formal verification tasks, where it significantly accelerates the performance of traditional formal verification tools using computer algebra, demonstrated over four orders of magnitude runtime improvements. |
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| AbstractList | Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically, reasoning datapath and adder tree in bit-blasted Boolean networks is particularly crucial for verification and synthesis, and challenging. Conventional approaches either fail to accurately (exactly) identify the function blocks of the designs in gate-level netlist with structural hashing and symbolic propagation, or their reasoning performance is highly sensitive to structure modifications caused by technology mapping or logic optimization. This paper introduces BoolE, an exact symbolic reasoning framework for Boolean netlists using equality saturation. BoolE optimizes scalability and performance by integrating domain-specific Boolean ruleset for term rewriting. We incorporate a novel extraction algorithm into BoolE to enhance its structural insight and computational efficiency, which adeptly identifies and captures multi-input, multi-output high-level structures (e.g., full adder) in the reconstructed e-graph. Our experiments show that BoolE surpasses state-of-the-art symbolic reasoning baselines, including the conventional functional approach (ABC) and machine learning-based method (Gamora). Specifically, we evaluated its performance on various multiplier architecture with different configurations. Our results show that BoolE identifies 3.53 \times and 3.01 \times more exact full adders than ABC in carry-save array and Booth-encoded multipliers, respectively. Additionally, we integrated BoolE into multiplier formal verification tasks, where it significantly accelerates the performance of traditional formal verification tools using computer algebra, demonstrated over four orders of magnitude runtime improvements. |
| Author | Hu, Qihao Chen, Chen Yin, Jiaqi Song, Zhan Yu, Cunxi |
| Author_xml | – sequence: 1 givenname: Jiaqi surname: Yin fullname: Yin, Jiaqi email: jyin629@umd.edu organization: University of Maryland, College Park,College Park,US – sequence: 2 givenname: Zhan surname: Song fullname: Song, Zhan organization: University of Maryland, College Park,College Park,US – sequence: 3 givenname: Chen surname: Chen fullname: Chen, Chen organization: University of Maryland, College Park,College Park,US – sequence: 4 givenname: Qihao surname: Hu fullname: Hu, Qihao organization: University of Maryland, College Park,College Park,US – sequence: 5 givenname: Cunxi surname: Yu fullname: Yu, Cunxi email: cunxiyu@umd.edu organization: University of Maryland, College Park,College Park,US |
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| Snippet | Boolean symbolic reasoning for gate-level netlists is a critical step in verification, logic and datapath synthesis, and hardware security. Specifically,... |
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| SubjectTerms | Adders Cognition Formal verification Hardware security Learning systems Logic gates Machine learning algorithms Optimization Runtime Scalability |
| Title | BoolE: Exact Symbolic Reasoning via Boolean Equality Saturation |
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