DenSparSA: A Balanced Systolic Array Approach for Dense and Sparse Matrix Multiplication

Numerous studies have proposed hardware architectures to accelerate sparse matrix multiplication, but these approaches often incur substantial area and power overhead, significantly compromising their usage in dense scenarios. On the other hand, systolic arrays deliver high efficiency for dense matr...

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Vydané v:	2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7
Hlavní autori:	Wang, Ziheng, Sun, Ruiqi, He, Xin, Ma, Tianrui, Zou, An
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 22.06.2025
Predmet:	Acceleration Computational efficiency Computer architecture Distance measurement Hands Hardware Microarchitecture Neural Network Neural networks Sparse matrices Sparsity Switching circuits Systolic arrays
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