Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving

The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and verification. However, existing SAT solvers, optimized for Conjunctive Normal Form (CNF), often struggle with the intrinsic complexity of circuit s...

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Bibliographic Details

Published in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) pp. 1 - 7
Main Authors:	Shi, Zhengyuan, Tang, Tiebing, Zhu, Jiaying, Khan, Sadaf, Zhen, Hui-Ling, Yuan, Mingxuan, Chu, Zhufei, Xu, Qiang
Format:	Conference Proceeding
Language:	English
Published:	IEEE 22.06.2025
Subjects:	Benchmark testing Complexity theory Design automation Integrated circuit synthesis Logic Optimization Reinforcement learning Runtime Table lookup Technological innovation
Online Access:	Get full text
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