Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving
The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and verification. However, existing SAT solvers, optimized for Conjunctive Normal Form (CNF), often struggle with the intrinsic complexity of circuit s...
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| Vydáno v: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7 |
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IEEE
22.06.2025
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| Abstract | The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and verification. However, existing SAT solvers, optimized for Conjunctive Normal Form (CNF), often struggle with the intrinsic complexity of circuit structures when directly applied to CSAT instances. To address this challenge, we propose a novel preprocessing framework that leverages advanced logic synthesis techniques and a reinforcement learning (RL) agent to optimize CSAT problem instances. The framework introduces a cost-customized Look-Up Table (LUT) mapping strategy that prioritizes solving efficiency, effectively transforming circuits into simplified forms tailored for SAT solvers. Our method achieves significant runtime reductions across diverse industrial-scale CSAT benchmarks, seamlessly integrating with state-of-the-art SAT solvers. Extensive experimental evaluations demonstrate up to 63 \% reduction in solving time compared to conventional approaches, highlighting the potential of EDAdriven innovations to advance SAT-solving capabilities. |
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| AbstractList | The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and verification. However, existing SAT solvers, optimized for Conjunctive Normal Form (CNF), often struggle with the intrinsic complexity of circuit structures when directly applied to CSAT instances. To address this challenge, we propose a novel preprocessing framework that leverages advanced logic synthesis techniques and a reinforcement learning (RL) agent to optimize CSAT problem instances. The framework introduces a cost-customized Look-Up Table (LUT) mapping strategy that prioritizes solving efficiency, effectively transforming circuits into simplified forms tailored for SAT solvers. Our method achieves significant runtime reductions across diverse industrial-scale CSAT benchmarks, seamlessly integrating with state-of-the-art SAT solvers. Extensive experimental evaluations demonstrate up to 63 \% reduction in solving time compared to conventional approaches, highlighting the potential of EDAdriven innovations to advance SAT-solving capabilities. |
| Author | Chu, Zhufei Xu, Qiang Shi, Zhengyuan Zhen, Hui-Ling Tang, Tiebing Yuan, Mingxuan Zhu, Jiaying Khan, Sadaf |
| Author_xml | – sequence: 1 givenname: Zhengyuan surname: Shi fullname: Shi, Zhengyuan organization: The Chinese University of Hong Kong,Department of Computer Science and Engineering,Hong Kong,S.A.R – sequence: 2 givenname: Tiebing surname: Tang fullname: Tang, Tiebing organization: The Chinese University of Hong Kong,Department of Computer Science and Engineering,Hong Kong,S.A.R – sequence: 3 givenname: Jiaying surname: Zhu fullname: Zhu, Jiaying organization: The Chinese University of Hong Kong,Department of Computer Science and Engineering,Hong Kong,S.A.R – sequence: 4 givenname: Sadaf surname: Khan fullname: Khan, Sadaf organization: The Chinese University of Hong Kong,Department of Computer Science and Engineering,Hong Kong,S.A.R – sequence: 5 givenname: Hui-Ling surname: Zhen fullname: Zhen, Hui-Ling organization: Noah's Ark Lab, Huawei,Hong Kong,S.A.R – sequence: 6 givenname: Mingxuan surname: Yuan fullname: Yuan, Mingxuan organization: Noah's Ark Lab, Huawei,Hong Kong,S.A.R – sequence: 7 givenname: Zhufei surname: Chu fullname: Chu, Zhufei organization: Ningbo University,Faculty of Electrical Engineering and Computer Science,Ningbo,China – sequence: 8 givenname: Qiang surname: Xu fullname: Xu, Qiang email: qxu@cse.cuhk.edu.hk organization: The Chinese University of Hong Kong,Department of Computer Science and Engineering,Hong Kong,S.A.R |
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| Snippet | The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and... |
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| SubjectTerms | Benchmark testing Complexity theory Design automation Integrated circuit synthesis Logic Optimization Reinforcement learning Runtime Table lookup Technological innovation |
| Title | Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving |
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