ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring

In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a t...

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Veröffentlicht in:	2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 7
Hauptverfasser:	Tsaras, Dimitris, Li, Xing, Chen, Lei, Xie, Zhiyao, Yuan, Mingxuan
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 22.06.2025
Schlagworte:	AND-Invert Graph Benchmark testing Design automation Geophysical measurement techniques Ground penetrating radar Logic Logic gates Logic Refactoring Logic Synthesis Machine learning Optimization Pruning Redundancy Tuning
Online-Zugang:	Volltext
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