ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a t...
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| Vydané v: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) s. 1 - 7 |
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22.06.2025
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| Abstract | In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a task which often fails 98 \% on average. Prior research has sought to mitigate computational cost through parallelization. In contrast, our approach leverages a classifier to prune unsuccessful cuts preemptively, thus eliminating unnecessary resynthesis operations. Experiments on the refactor operator using the EPFL benchmark suite and 10 large industrial designs demonstrate that this technique can speedup logic optimization by 3.9 \times on average compared with the state-of-the-art ABC implementation. |
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| AbstractList | In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation demands are high. Operators such as refactor conventionally form iterative cuts for each node, striving for a more compact representation - a task which often fails 98 \% on average. Prior research has sought to mitigate computational cost through parallelization. In contrast, our approach leverages a classifier to prune unsuccessful cuts preemptively, thus eliminating unnecessary resynthesis operations. Experiments on the refactor operator using the EPFL benchmark suite and 10 large industrial designs demonstrate that this technique can speedup logic optimization by 3.9 \times on average compared with the state-of-the-art ABC implementation. |
| Author | Li, Xing Tsaras, Dimitris Xie, Zhiyao Yuan, Mingxuan Chen, Lei |
| Author_xml | – sequence: 1 givenname: Dimitris surname: Tsaras fullname: Tsaras, Dimitris organization: The Hong Kong University of Science and Technology,Hong Kong – sequence: 2 givenname: Xing surname: Li fullname: Li, Xing organization: Noah's Ark Lab,Huawei,Hong Kong – sequence: 3 givenname: Lei surname: Chen fullname: Chen, Lei email: lc.leichen@huawei.com organization: Noah's Ark Lab,Huawei,Hong Kong – sequence: 4 givenname: Zhiyao surname: Xie fullname: Xie, Zhiyao organization: The Hong Kong University of Science and Technology,Hong Kong – sequence: 5 givenname: Mingxuan surname: Yuan fullname: Yuan, Mingxuan organization: Noah's Ark Lab,Huawei,Hong Kong |
| BookMark | eNo1j1FLwzAUhSPog879A5H8gc4kN2lyfRu1U6GwoXsfWXI7A5pK2z3031tQnw7nO_DBuWGXucvE2L0UKykFPjytqxKcxpUSysxIgnIIF2yJFh2ANAKEdtesqpvNI6_bNoVEeeRNd0qBv095_KAhDfw48V1_zimf-BvFc44-h4mnPLfWh7Hr5-WWXbX-c6DlXy7YflPvq5ei2T6_Vuum8NLiWCgsHZKjIKyzCi2QbSEqRWBI09EKQhmhjEZJAG_AaNBB-tKgFoEIFuzuV5uI6PDdpy_fT4f_a_ADBk9G9w |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1109/DAC63849.2025.11132893 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| EISBN | 9798331503048 |
| EndPage | 7 |
| ExternalDocumentID | 11132893 |
| Genre | orig-research |
| GroupedDBID | 6IE 6IH CBEJK RIE RIO |
| ID | FETCH-LOGICAL-a179t-29689e8ec07872973e7f3d22e35e4eb70e91d36d52133a535434c1a65940cee3 |
| IEDL.DBID | RIE |
| IngestDate | Wed Oct 01 07:05:15 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-a179t-29689e8ec07872973e7f3d22e35e4eb70e91d36d52133a535434c1a65940cee3 |
| PageCount | 7 |
| ParticipantIDs | ieee_primary_11132893 |
| PublicationCentury | 2000 |
| PublicationDate | 2025-June-22 |
| PublicationDateYYYYMMDD | 2025-06-22 |
| PublicationDate_xml | – month: 06 year: 2025 text: 2025-June-22 day: 22 |
| PublicationDecade | 2020 |
| PublicationTitle | 2025 62nd ACM/IEEE Design Automation Conference (DAC) |
| PublicationTitleAbbrev | DAC |
| PublicationYear | 2025 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| Score | 2.295249 |
| Snippet | In electronic design automation, logic optimization operators play a crucial role in minimizing the gate count of logic circuits. However, their computation... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | AND-Invert Graph Benchmark testing Design automation Geophysical measurement techniques Ground penetrating radar Logic Logic gates Logic Refactoring Logic Synthesis Machine learning Optimization Pruning Redundancy Tuning |
| Title | ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring |
| URI | https://ieeexplore.ieee.org/document/11132893 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwELVoxcAEiCK-5YHVbWLHdsyGSiKGqqqgQ7fKsS9SlxT1A6n_nrObghgY2Bw7Vpxzkne63LtHyKOpXVo5q5gAW7OsksCsNJZpmVmdGJsnPhZxHenxOJ_NzKQlq0cuDADE5DPoh2b8l--XbhtCZYMoi44A2yEdrdWerNWyftPEDF6eh_g0ZYF-wmX_cPIv2ZSIGuXpP693Rno__Ds6-UaWc3IEzQUZFqPyiRax5ANOo0El2dH3XYMu3HqxptUO52xDmIO-QeCGhe8mXTR4tBfVwZEemZbFdPjKWgkEZvFN2TBuVG4gB4dIroPMFOhaeM5BSMig0gmY1AvlEYSFsFIEoqhLrZImS3CR4pJ0m2UDV4RWHF3Dmnv0WGwmUzBeOKVqE8r9VKDdNekFA8w_9kUu5od7v_mj_5acBDOHrCnO70h3s9rCPTl2n5vFevUQt-YLv_2P4g |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV09T8MwED1BQYIJEEV844HVbeKPOGZDpVURoaqgQ7fKcS5SlxQ1LVL_PbbbghgY2Bw7Vpxzkne63LsHcK9LG-fWJJSjKanIJVIjtaFKCqMibdKoCEVcMzUYpOOxHm7I6oELg4gh-Qxbvhn-5Rczu_ShsnaQRXcAuwt7UggWrelaG95vHOn202PHPU_CE1CYbG1P_yWcEnCjd_TPKx5D84eBR4bf2HICO1idQqeb9R5INxR9cNOI10m25H1VOSeuntYkX7k5Sx_oIG_o2WH-y0mmlTtay-q4kSaMet1Rp083IgjUuHdlQZlOUo0pWoflygtNoSp5wRhyiQJzFaGOC54UDoY5N5J7qqiNTSK1iNwi-Rk0qlmF50By5pzDkhXOZzFCxqgLbpOk1L7gT47KXkDTG2DysS5zMdne--Uf_Xdw0B-9ZpPsefByBYfe5D6HirFraCzmS7yBffu5mNbz27BNX2_Ikyk |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2025+62nd+ACM%2FIEEE+Design+Automation+Conference+%28DAC%29&rft.atitle=ELF%3A+Efficient+Logic+Synthesis+by+Pruning+Redundancy+in+Refactoring&rft.au=Tsaras%2C+Dimitris&rft.au=Li%2C+Xing&rft.au=Chen%2C+Lei&rft.au=Xie%2C+Zhiyao&rft.date=2025-06-22&rft.pub=IEEE&rft.spage=1&rft.epage=7&rft_id=info:doi/10.1109%2FDAC63849.2025.11132893&rft.externalDocID=11132893 |