SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain. The lack of circuit data has become the primary bottleneck in developing AI-assisted IC design methods. In this work, w...
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| Veröffentlicht in: | 2025 62nd ACM/IEEE Design Automation Conference (DAC) S. 1 - 7 |
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22.06.2025
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| Abstract | In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain. The lack of circuit data has become the primary bottleneck in developing AI-assisted IC design methods. In this work, we make the first attempt, SynCircuit, to generate new synthetic circuits with valid functionalities in the HDL format.SynCircuit automatically generates synthetic data using a framework with three innovative steps: 1) We propose a customized diffusion-based generative model to resolve the Directed Cyclic Graph (DCG) generation task, which has not been well explored in the AI community. 2) To ensure our circuit is valid, we enforce the circuit constraints by refining the initial graph generation outputs. 3) The Monte Carlo tree search (MCTS) method further optimizes the logic redundancy in the generated graph. Experimental results demonstrate that our proposed SynCircuit can generate more realistic synthetic circuits and enhance ML model performance in downstream circuit design tasks. |
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| AbstractList | In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain. The lack of circuit data has become the primary bottleneck in developing AI-assisted IC design methods. In this work, we make the first attempt, SynCircuit, to generate new synthetic circuits with valid functionalities in the HDL format.SynCircuit automatically generates synthetic data using a framework with three innovative steps: 1) We propose a customized diffusion-based generative model to resolve the Directed Cyclic Graph (DCG) generation task, which has not been well explored in the AI community. 2) To ensure our circuit is valid, we enforce the circuit constraints by refining the initial graph generation outputs. 3) The Monte Carlo tree search (MCTS) method further optimizes the logic redundancy in the generated graph. Experimental results demonstrate that our proposed SynCircuit can generate more realistic synthetic circuits and enhance ML model performance in downstream circuit design tasks. |
| Author | Liu, Shang Fang, Wenji Xie, Zhiyao Wang, Jing |
| Author_xml | – sequence: 1 givenname: Shang surname: Liu fullname: Liu, Shang email: sliudx@connect.ust.hk organization: Hong Kong University of Science and Technology – sequence: 2 givenname: Jing surname: Wang fullname: Wang, Jing email: jwangjw@connect.ust.hk organization: Hong Kong University of Science and Technology – sequence: 3 givenname: Wenji surname: Fang fullname: Fang, Wenji email: wfang838@connect.ust.hk organization: Hong Kong University of Science and Technology – sequence: 4 givenname: Zhiyao surname: Xie fullname: Xie, Zhiyao email: eezhiyao@ust.hk organization: Hong Kong University of Science and Technology |
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| Snippet | In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially... |
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| SubjectTerms | Circuit synthesis Design automation Design methodology Hardware design languages Integrated circuit modeling Logic Monte Carlo methods Redundancy Refining Synthetic data |
| Title | SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits |
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