The synthesis of robust polynomial arithmetic with stochastic logic

As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challenging. Indeed, mounting concerns over noise and uncertainty in signal values motivate a new approach: the design of stochas...

Full description

Saved in:
Bibliographic Details
Published in:2008 45th ACM/IEEE Design Automation Conference pp. 648 - 653
Main Authors: Qian, Weikang, Riedel, Marc D.
Format: Conference Proceeding
Language:English
Published: New York, NY, USA ACM 08.06.2008
IEEE
Series:ACM Conferences
Subjects:
Arithmetic
Circuits
Hardware > Hardware test
Hardware > Integrated circuits > Logic circuits > Combinational circuits
Hardware > Robustness
Logic
Polynomial Arithmetic
Polynomials
Probabilistic Logic
Robustness
Signal processing
Signal synthesis
Stochastic Logic
Stochastic processes
Stochastic resonance
Uncertainty
probabilistic logic
stochastic logic
polynomial arithmetic
ISBN:1605581151, 9781605581156
ISSN:0738-100X
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challenging. Indeed, mounting concerns over noise and uncertainty in signal values motivate a new approach: the design of stochastic logic, that is to say, digital circuitry that processes signals probabilistically, and so can cope with errors and uncertainty. In this paper, we present a general methodology for synthesizing stochastic logic for the computation of polynomial arithmetic functions, a category that is important for applications such as digital signal processing. The method is based on converting polynomials into a particular mathematical form --- Bernstein polynomials --- and then implementing the computation with stochastic logic. The resulting logic processes serial or parallel streams that are random at the bit level. In the aggregate, the computation becomes accurate, since the results depend only on the precision of the statistics. Experiments show that our method produces circuits that are highly tolerant of errors in the input stream, while the area-delay product of the circuit is comparable to that of deterministic implementations.
ISBN:1605581151
9781605581156
ISSN:0738-100X
DOI:10.1145/1391469.1391636