Scratchpad memory design alternative for cache on-chip memory in embedded systems

In this paper we address the problem of on-chip memory selection for computationally intensive applications, by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache sizes are computed using the CACTI tool while performance was evaluated using t...

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Vydáno v:10th International Symposium on Hardware/Software Codesign s. 73 - 78
Hlavní autoři: Banakar, Rajeshwari, Steinke, Stefan, Lee, Bo-Sik, Balakrishnan, M., Marwedel, Peter
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 06.05.2002
IEEE
Edice:ACM Conferences
Témata:
Cache memory
Computational modeling
Computer science
Computer systems organization > Embedded and cyber-physical systems
Computer systems organization > Real-time systems
Computing methodologies > Symbolic and algebraic manipulation > Computer algebra systems
Digital signal processing chips
Embedded system
Energy consumption
Hardware > Integrated circuits > Semiconductor memory > Dynamic memory
Information systems > Data management systems > Database management system engines
Permission
Random access memory
Speech processing
System-on-a-chip
ISBN:1581135424, 9781581135428
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Shrnutí:In this paper we address the problem of on-chip memory selection for computationally intensive applications, by proposing scratch pad memory as an alternative to cache. Area and energy for different scratch pad and cache sizes are computed using the CACTI tool while performance was evaluated using the trace results of the simulator. The target processor chosen for evaluation was AT91M40400. The results clearly establish scratehpad memory as a low power alternative in most situations with an average energy reducation of 40%. Further the average area-time reduction for the seratchpad memory was 46% of the cache memory.
ISBN:1581135424
9781581135428
DOI:10.1145/774789.774805