FFT program generation for shared memory SMP and multicore

The chip maker's response to the approaching end of CPU frequency scaling are multicore systems, which offer the same programming paradigm as traditional shared memory platforms but have different performance characteristics. This situation considerably increases the burden on library developer...

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Vydáno v:Conference on High Performance Networking and Computing: Proceedings of the 2006 ACM/IEEE conference on Supercomputing; 11-17 Nov. 2006 s. 115 - es
Hlavní autoři: Franchetti, Franz, Voronenko, Yevgen, Püschel, Markus
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: New York, NY, USA ACM 11.11.2006
Edice:ACM Conferences
Témata:
Hardware > Integrated circuits
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
Mathematics of computing > Mathematical analysis > Functional analysis > Approximation
Mathematics of computing > Mathematical analysis > Numerical analysis > Computation of transforms
Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis
chip multiprocessor
fast fourier transform
automatic parallelization
multicore
shared memory
ISBN:0769527000, 9780769527000
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Shrnutí:The chip maker's response to the approaching end of CPU frequency scaling are multicore systems, which offer the same programming paradigm as traditional shared memory platforms but have different performance characteristics. This situation considerably increases the burden on library developers and strengthens the case for automatic performance tuning frameworks like Spiral, a program generator and optimizer for linear transforms such as the discrete Fourier transform (DFT). We present a shared memory extension of Spiral. The extension within Spiral consists of a rewriting system that manipulates the structure of transform algorithms to achieve load balancing and avoids false sharing, and of a backend to generate multithreaded code. Application to the DFT produces a novel class of algorithms suitable for multicore systems as validated by experimental results: we demonstrate a parallelization speed-up already for sizes that fit into L1 cache and compare favorably to other DFT libraries across all small and midsize DFTs and considered platforms.
Bibliografie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:0769527000
9780769527000
DOI:10.1145/1188455.1188575