A formal executable semantics of Verilog

This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tool...

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Vydané v:2010 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign s. 179 - 188
Hlavní autori: Meredith, Patrick, Katelman, Michael, Meseguer, Jose, Rosu, Grigore
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.07.2010
Predmet:
Computational modeling
Delay
Equations
Hardware design languages
Integrated circuit modeling
Mathematical model
Semantics
ISBN:9781424478859, 1424478855
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Shrnutí:This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operational-style within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.
ISBN:9781424478859
1424478855
DOI:10.1109/MEMCOD.2010.5558634