A formal executable semantics of Verilog

This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tool...

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Bibliographic Details

Published in:	2010 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign pp. 179 - 188
Main Authors:	Meredith, Patrick, Katelman, Michael, Meseguer, Jose, Rosu, Grigore
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.07.2010
Subjects:	Computational modeling Delay Equations Hardware design languages Integrated circuit modeling Mathematical model Semantics
ISBN:	9781424478859, 1424478855
Online Access:	Get full text
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