A formal executable semantics of Verilog

This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tool...

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Vydané v:	2010 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign s. 179 - 188
Hlavní autori:	Meredith, Patrick, Katelman, Michael, Meseguer, Jose, Rosu, Grigore
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 01.07.2010
Predmet:	Computational modeling Delay Equations Hardware design languages Integrated circuit modeling Mathematical model Semantics
ISBN:	9781424478859, 1424478855
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