A formal executable semantics of Verilog

This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tool...

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Veröffentlicht in:2010 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign S. 179 - 188
Hauptverfasser: Meredith, Patrick, Katelman, Michael, Meseguer, Jose, Rosu, Grigore
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.07.2010
Schlagworte:
Computational modeling
Delay
Equations
Hardware design languages
Integrated circuit modeling
Mathematical model
Semantics
ISBN:9781424478859, 1424478855
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Abstract This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operational-style within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.
AbstractList This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous reference augmenting the prose of the official language standard, and ultimately to aid developers of Verilog-based tools; e.g., simulators, test generators, and verification tools. Our semantics applies equally well to both synthesizeable and behavioral designs and is given in a familiar, operational-style within a logic providing important additional benefits above and beyond static formalization. In particular, it is executable and searchable so that one can ask questions about how a, possibly nondeterministic, Verilog program can legally behave under the formalization. The formalization should not be seen as the final word on Verilog, but rather as a starting point and basis for community discussions on the Verilog semantics.
Author Katelman, Michael
Rosu, Grigore
Meseguer, Jose
Meredith, Patrick
Author_xml – sequence: 1
  givenname: Patrick
  surname: Meredith
  fullname: Meredith, Patrick
  email: pmeredit@uiuc.edu
  organization: Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA
– sequence: 2
  givenname: Michael
  surname: Katelman
  fullname: Katelman, Michael
  email: katelman@uiuc.edu
  organization: Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA
– sequence: 3
  givenname: Jose
  surname: Meseguer
  fullname: Meseguer, Jose
  email: meseguer@uiuc.edu
  organization: Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA
– sequence: 4
  givenname: Grigore
  surname: Rosu
  fullname: Rosu, Grigore
  email: grosu@uiuc.edu
  organization: Dept. of Comput. Sci., Univ. of Illinois at Urbana-Champaign, Champaign, IL, USA
BookMark eNo1T8lOwzAUNKJI0JIv6MVHLil2_BzbxyqURWrVS-FavbjPKCgLioMEf48lylxGM4dZ5mzWDz0xtpRiJaVw97vNrto_rAqRDK21LRVcsLmEAsDYpC5Z5oz919pdsyzGD5EAugBlb9jdmodh7LDl9E3-a8K6JR6pw35qfORD4G80Nu3wfsuuAraRsjMv2Ovj5lA959v900u13uYojZhyaUoAH-AEBKEuU6csrfBagNcoIBjrTRDKOh_SBnQ2WNTFCWrwArVCtWDLv9yGiI6fY9Ph-HM8n1O_8fNDKg
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/MEMCOD.2010.5558634
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Electronic Library (IEL)
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Computer Science
EISBN 1424478863
9781424478866
EndPage 188
ExternalDocumentID 5558634
Genre orig-research
GroupedDBID 6IE
6IF
6IK
6IL
6IN
AAJGR
AAWTH
ACM
ADFMO
ALMA_UNASSIGNED_HOLDINGS
APO
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
GUFHI
IEGSK
IERZE
LHSKQ
OCL
RIE
RIL
ID FETCH-LOGICAL-a170t-17644cf4d4e4fb68591680c504c5a04f78c7f0389cf045a98f8a52d4b4c0a53a3
IEDL.DBID RIE
ISBN 9781424478859
1424478855
IngestDate Wed Aug 27 02:52:12 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-a170t-17644cf4d4e4fb68591680c504c5a04f78c7f0389cf045a98f8a52d4b4c0a53a3
PageCount 10
ParticipantIDs ieee_primary_5558634
PublicationCentury 2000
PublicationDate 2010-July
PublicationDateYYYYMMDD 2010-07-01
PublicationDate_xml – month: 07
  year: 2010
  text: 2010-July
PublicationDecade 2010
PublicationTitle 2010 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign
PublicationTitleAbbrev MEMCOD
PublicationYear 2010
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0000452438
Score 1.6110952
Snippet This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and...
SourceID ieee
SourceType Publisher
StartPage 179
SubjectTerms Computational modeling
Delay
Equations
Hardware design languages
Integrated circuit modeling
Mathematical model
Semantics
Title A formal executable semantics of Verilog
URI https://ieeexplore.ieee.org/document/5558634
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEJ4A8eAJFYzv9ODBgysLO912jwYhXkAOariRMjtNSBQMuxh_vu3ugjHxYk9tD5M-p512vm8ArmOrNRojg55BZ6AwY5CEaRrMyaVeZN0NAotgE2o81tNpMqnB7Q4Lw8yF8xnf-Wzxl5-uaOOfyjqemyqOsA51peISq7V7T_HU4BjpLXbLWXZSbimdqnJSsQ51w6QzGoz6Tw-la1cl9ld8leJ4GTb_17ADaP_g9MRkdwIdQo2XR9DcBmoQ1b5twc29KO6mb4K_mDa5h0uJjN_dqC4oEysrXt1CdFqwDS_DwXP_MahCJASmq8Lc0zsiksUUGe089mR0sQ5JhkjShGiVJmU9hx5ZN0Am0VYb2UtxjhQaGZnoGBrL1ZJPQFiibiqZnUjCCI0zja1TPoYksoooPYWW7_jso2TBmFV9Pvu7-hz2y39279h6AY18veFL2KPPfJGtr4qp-wYyXpUN
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LTwIxEJ4gmugJFYxve_DgwZWyO93tHg1CMAJyQMONlO40IVEwsBh_vu3ugjHxYk9tD5M-p512vm8ArkMjJSolPF-hNVCI0It5kngTbZMfGHuDwCzYRNTvy9EoHpTgdoOFIaLM-YzuXDb7y0_meuWeyuqOmyoMcAu2BaLPc7TW5kXFkYNjINfoLWvbCbEmdSrKccE71OBxvdfqNZ8fcueuQvCvCCvZAdOu_K9p-1D7QeqxweYMOoASzQ6hsg7VwIqdW4Wbe5bdTt8YfZFepQ4wxZb0bsd1qpdsbtirXYpWD9bgpd0aNjteESTBU42Ip47gEVEbTJDQTEJHRxdKrgVHLRRHE0kdGceip40dIBVLI5XwE5yg5koEKjiC8mw-o2NgRutGIoisSI0BKmscG6t-lBZIUaCTE6i6jo8_ch6McdHn07-rr2C3M-x1x93H_tMZ7OW_7s7N9RzK6WJFF7CjP9PpcnGZTeM3K3-YVA
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2010+8th+IEEE%2FACM+International+Conference+on+Formal+Methods+and+Models+for+Codesign&rft.atitle=A+formal+executable+semantics+of+Verilog&rft.au=Meredith%2C+Patrick&rft.au=Katelman%2C+Michael&rft.au=Meseguer%2C+Jose&rft.au=Rosu%2C+Grigore&rft.date=2010-07-01&rft.pub=IEEE&rft.isbn=9781424478859&rft.spage=179&rft.epage=188&rft_id=info:doi/10.1109%2FMEMCOD.2010.5558634&rft.externalDocID=5558634
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424478859/lc.gif&client=summon&freeimage=true
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424478859/mc.gif&client=summon&freeimage=true
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424478859/sc.gif&client=summon&freeimage=true