Methods for true power minimization

This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These savings are obtained by using gate sizing, supply voltage, and threshold voltage optimization, to minimi...

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Veröffentlicht in:Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design S. 35 - 42
Hauptverfasser: Brodersen, Robert W., Horowitz, Mark A., Markovic, Dejan, Nikolic, Borivoje, Stojanovic, Vladimir
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 10.11.2002
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Applied sciences
Circuit properties
Design. Technologies. Operation analysis. Testing
Digital circuits
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Hardware > Emerging technologies
Hardware > Integrated circuits
Hardware > Integrated circuits > Interconnect > Input > output circuits
Integrated circuits
Integrated circuits by function (including memories and processors)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Potential energy
Performance evaluation
Inverter
Voltage threshold
Arithmetic circuit
Circuit design
Power circuit
Random access memory
Decoding circuit
Adder
Physical properties
Optimization
Circuit architecture
Dimensioning
Power consumption
SRAM chips
Integrated circuit
Computer aided design
ISBN:0780376072, 9780780376076
ISSN:1092-3152
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Beschreibung
Zusammenfassung:This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These savings are obtained by using gate sizing, supply voltage, and threshold voltage optimization, to minimize energy consumption subject to a delay constraint. The true power minimization is achieved when the energy reduction potentials of all tuning variables are balanced. We derive the sensitivity of energy to delay for each of the tuning variables connecting its energy saving potential to the physical properties of the circuit. This helps to develop understanding of optimization performance and identify the most efficient techniques for energy reduction. The optimizations are applied to some examples that span typical circuit topologies including inverter chains, SRAM decoders, and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that achieving peak performance is expensive in terms of energy. Energy savings of about 50% can be achieved without delay penalty with the balancing of sizes, supplies, and thresholds.
ISBN:0780376072
9780780376076
ISSN:1092-3152
DOI:10.1145/774572.774578