Taming the killer microsecond

Modern applications require access to vast datasets at low latencies. Emerging memory technologies can enable faster access to significantly larger volumes of data than what is possible today. However, these memory technologies have a significant caveat: their random access latency falls in a range...

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Vydáno v:2018 51st Annual IEEE ACM International Symposium on Microarchitecture (MICRO) s. 627 - 640
Hlavní autoři: Cho, Shenghsun, Suresh, Amoghavarsha, Palit, Tapti, Ferdman, Michael, Honarmand, Nima
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: Piscataway, NJ, USA IEEE Press 20.10.2018
IEEE
Edice:ACM Conferences
Témata:
Data intensive applications
Emerging storage
FPGA
General and reference
General and reference > Cross-computing tools and techniques
General and reference > Cross-computing tools and techniques > Performance
Hardware
Kernel
Killer microseconds
Performance evaluation
Prefetching
Random access memory
Servers
data-intensive applications
FPGA
emerging storage
killer microseconds
ISBN:9781538662403, 153866240X
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Shrnutí:Modern applications require access to vast datasets at low latencies. Emerging memory technologies can enable faster access to significantly larger volumes of data than what is possible today. However, these memory technologies have a significant caveat: their random access latency falls in a range that cannot be effectively hidden using current hardware and software latency-hiding techniques---namely, the microsecond range. Finding the root cause of this "Killer Microsecond" problem, is the subject of this work. Our goal is to answer the critical question of why existing hardware and software cannot hide microsecond-level latencies, and whether drastic changes to existing platforms are necessary to utilize microsecond-latency devices effectively. We use an FPGA-based microsecond-latency device emulator, a carefully-crafted microbenchmark, and three open-source data-intensive applications to show that existing systems are indeed incapable of effectively hiding such latencies. However, after uncovering the root causes of the problem, we show that simple changes to existing systems are sufficient to support microsecond-latency devices. In particular, we show that by replacing on-demand memory accesses with prefetch requests followed by fast user-mode context switches (to increase access-level parallelism) and enlarging hardware queues that track in-flight accesses (to accommodate many parallel accesses), conventional architectures can effectively hide microsecond-level latencies, and approach the performance of DRAM-based implementations of the same applications. In other words, we show that successful usage of microsecond-level devices is not predicated on drastically new hardware and software architectures.
ISBN:9781538662403
153866240X
DOI:10.1109/MICRO.2018.00057