Topology-based optimization of maximal sustainable throughput in a latency-insensitive system

We consider the problem of optimizing the performance of a latency-insensitive system (LIS) where the addition of backpressure has caused throughput degradation. Previous works have addressed the problem of LIS performance in different ways. In particular, the insertion of relay stations and the siz...

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Bibliographic Details
Published in:	2007 44th ACM/IEEE Design Automation Conference pp. 410 - 415
Main Authors:	Collins, Rebecca L., Carloni, Luca P.
Format:	Conference Proceeding
Language:	English
Published:	New York, NY, USA ACM 04.06.2007 IEEE
Series:	ACM Conferences
Subjects:	Buffer storage Clocks Computer science Concurrent computing Degradation Hardware > Electronic design automation > High-level and register-transfer level synthesis Latency-Insensitive Design Performance Analysis. General Terms Algorithms Pipeline processing Relays Theory of computation > Models of computation Throughput Topology Wire latency-insensitive design performance analysis
ISBN:	1595936270, 9781595936271
ISSN:	0738-100X
Online Access:	Get full text
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