Energy efficient implementation of parallel CMOS multipliers with improved compressors

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16×16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targ...

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Bibliographic Details

Published in:	2010 ACM/IEEE International Symposium on Low Power Electronics and Design pp. 147 - 152
Main Authors:	Baran, Dursun, Aktan, Mustafa, Oklobdzija, Vojin G.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.08.2010
Subjects:	Adders Arithmetic and Logic Structures Booth Encoding CMOS integrated circuits CMOS technology Compressors Delay High-Speed Arithmetic Logic gates Low-Power Design Mirrors VLSI
ISBN:	1424485886, 9781424485888
Online Access:	Get full text
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