Energy efficient implementation of parallel CMOS multipliers with improved compressors

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16×16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targ...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	2010 ACM/IEEE International Symposium on Low Power Electronics and Design S. 147 - 152
Hauptverfasser:	Baran, Dursun, Aktan, Mustafa, Oklobdzija, Vojin G.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.08.2010
Schlagworte:	Adders Arithmetic and Logic Structures Booth Encoding CMOS integrated circuits CMOS technology Compressors Delay High-Speed Arithmetic Logic gates Low-Power Design Mirrors VLSI
ISBN:	1424485886, 9781424485888
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!