Energy efficient implementation of parallel CMOS multipliers with improved compressors

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16×16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targ...

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Bibliographic Details
Published in:2010 ACM/IEEE International Symposium on Low Power Electronics and Design pp. 147 - 152
Main Authors: Baran, Dursun, Aktan, Mustafa, Oklobdzija, Vojin G.
Format: Conference Proceeding
Language:English
Published: IEEE 01.08.2010
Subjects:
Adders
Arithmetic and Logic Structures
Booth Encoding
CMOS integrated circuits
CMOS technology
Compressors
Delay
High-Speed Arithmetic
Logic gates
Low-Power Design
Mirrors
VLSI
ISBN:1424485886, 9781424485888
Online Access:Get full text
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Summary:Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16×16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targets. In addition, novel 3:2 and 4:2 compressors are presented to save energy at the same target delay. The proposed compressors provide up to 20% energy reduction depending on the target delay at 65nm CMOS technology. Non-Booth multiplier implemented with the proposed compressors provides performance advantage as the voltage is scaled from its nominal value. Further, we examined all designs in 45nm, 32nm and 22nm CMOS technology nodes.
ISBN:1424485886
9781424485888
DOI:10.1145/1840845.1840876