Qureshi, M. K., & Loh, G. H. (2012, December). Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 235-246. https://doi.org/10.1109/MICRO.2012.30
Chicago-Zitierstil (17. Ausg.)Qureshi, Moinuddin K., und Gabe H. Loh. "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design." 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Dec. 2012: 235-246. https://doi.org/10.1109/MICRO.2012.30.
MLA-Zitierstil (9. Ausg.)Qureshi, Moinuddin K., und Gabe H. Loh. "Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design." 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 2012, pp. 235-246, https://doi.org/10.1109/MICRO.2012.30.