A high performance split-radix FFT with constant geometry architecture

High performance hardware FFTs have numerous applications in instrumentation and communication systems. This paper describes a new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm is known to have lower mult...

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Bibliographic Details
Published in:Proceedings of the Conference on Design, Automation and Test in Europe pp. 1537 - 1542
Main Authors: Kwong, Joyce, Goel, Manish
Format: Conference Proceeding
Language:English
Published: San Jose, CA, USA EDA Consortium 12.03.2012
Series:ACM Conferences
Subjects:
Hardware > Hardware validation
Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific processors
Mathematics of computing > Mathematical analysis > Functional analysis > Approximation
Mathematics of computing > Mathematical analysis > Numerical analysis > Computation of transforms
Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis
ISBN:3981080181, 9783981080186
Online Access:Get full text
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Summary:High performance hardware FFTs have numerous applications in instrumentation and communication systems. This paper describes a new parallel FFT architecture which combines the split-radix algorithm with a constant geometry interconnect structure. The split-radix algorithm is known to have lower multiplicative complexity than both radix-2 and radix-4 algorithms. However, it conventionally involves an "L-shaped" butterfly datapath whose irregular shape has uneven latencies and makes scheduling difficult. This work proposes a split-radix datapath that avoids the L-shape. With this, the split-radix algorithm can be mapped onto a constant geometry interconnect structure in which the wiring in each FFT stage is identical, resulting in low multiplexing overhead. Further, we exploit the lower arithmetic complexity of split-radix to lower dynamic power, by gating the multipliers during trivial multiplications. The proposed FFT achieves 46% lower power than a parallel radix-4 design at 4.5GS/s when computing a 128-point real-valued transform.
ISBN:3981080181
9783981080186
DOI:10.5555/2492708.2493084