Power-efficient error-resiliency for H.264/AVC context-adaptive variable length coding

Technology scaling has led to unreliable computing hardware due to high susceptibility against soft errors. In this paper, we propose an error-resilient architecture for Context-Adaptive Variable Length Coding (CAVLC) in H.264/AVC. Due to its context-adaptive nature and intricate control flow CAVLC...

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Vydáno v:Proceedings of the Conference on Design, Automation and Test in Europe s. 697 - 702
Hlavní autoři: Shafique, Muhammad, Zatt, Bruno, Rehman, Semeen, Kriebel, Florian, Henkel, Jörg
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: San Jose, CA, USA EDA Consortium 12.03.2012
Edice:ACM Conferences
Témata:
Hardware > Emerging technologies
Hardware > Hardware validation
Mathematics of computing > Information theory
Mathematics of computing > Information theory > Coding theory
Security and privacy > Cryptography > Mathematical foundations of cryptography
ISBN:3981080181, 9783981080186
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Shrnutí:Technology scaling has led to unreliable computing hardware due to high susceptibility against soft errors. In this paper, we propose an error-resilient architecture for Context-Adaptive Variable Length Coding (CAVLC) in H.264/AVC. Due to its context-adaptive nature and intricate control flow CAVLC is very sensitive to soft errors. An error during the CAVLC process (especially during the context adaptation or in VLC tables) may result in severe mismatch between encoder and decoder. The primary goal in our error-resilient CAVLC architecture is to protect codeword/codelength tables and context adaptation in a reliable yet power efficient manner. For reducing the power overhead, the tables are partitioned in various sub-tables each protected with variable-sized parity. Moreover, for further power reduction, our approach incorporates state-retentive power-gating of different sub-tables at run time depending upon the statistical distribution of syntax elements. Compared to the unprotected case, our scheme provides a video quality improvement of 18dB (averaged over various fault injection cases and video sequences) at the cost of a 35% area overhead and 45% performance overhead due to the error-detection logic. However, partitioned sub-tables increase the potential for power-gating, thus bring a leakage energy saving of 58%. Compared to state-of-the-art table protection, our scheme provides 2x reduced area and performance overhead. For functional verification and area comparison, the architecture is prototyped on a Xilinx Virtex-5 FPGA, though not limited to it. For the soft errors experiments, evaluation of error-resiliency and power efficiency, we have developed a fault injection and simulation setup.
ISBN:3981080181
9783981080186
DOI:10.5555/2492708.2492885