A multilevel analytical placement for 3D ICs

In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and th...

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Veröffentlicht in:Proceedings of the 2009 Asia and South Pacific Design Automation Conference S. 361 - 366
Hauptverfasser: Cong, Jason, Luo, Guojie
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: Piscataway, NJ, USA IEEE Press 19.01.2009
Schriftenreihe:ACM Conferences
Schlagworte:
Information systems
Information systems > Data management systems
Information systems > Data management systems > Database administration
Information systems > Data management systems > Database administration > Data dictionaries
Theory of computation
Theory of computation > Design and analysis of algorithms
Theory of computation > Design and analysis of algorithms > Mathematical optimization
ISBN:9781424427482, 1424427487
Online-Zugang:Volltext
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Abstract In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and the problem can be solved by an analytical global placer. A key idea is to do the overlap removal and device layer assignment simultaneously by adding a density penalty function for both area & TS via density constraints. Experimental results show that this analytical placer in a multilevel framework is effective to achieve trade-offs between wirelength and TS via number. Compared to the recently published transformation-based 3D placement method [1], we are able to achieve on average 12% shorter wirelength and 29% fewer TS via compared to their cases with best wirelength; we are also able to achieve on average 20% shorter wirelength and 50% fewer TS via number compared to their cases with best TS via numbers.
AbstractList In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number subject to area density constraints. This approach relaxes the discrete layer assignments so that they are continuous in the z-direction and the problem can be solved by an analytical global placer. A key idea is to do the overlap removal and device layer assignment simultaneously by adding a density penalty function for both area & TS via density constraints. Experimental results show that this analytical placer in a multilevel framework is effective to achieve trade-offs between wirelength and TS via number. Compared to the recently published transformation-based 3D placement method [1], we are able to achieve on average 12% shorter wirelength and 29% fewer TS via compared to their cases with best wirelength; we are also able to achieve on average 20% shorter wirelength and 50% fewer TS via number compared to their cases with best TS via numbers.
Author Luo, Guojie
Cong, Jason
Author_xml – sequence: 1
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  fullname: Cong, Jason
  organization: University of California, Los Angeles and California NanoSystems Institute, Los Angeles, CA
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  givenname: Guojie
  surname: Luo
  fullname: Luo, Guojie
  organization: California NanoSystems Institute, Los Angeles, CA
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Snippet In this paper we propose a multilevel non-linear programming based 3D placement approach that minimizes a weighted sum of total wirelength and TS via number...
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StartPage 361
SubjectTerms Information systems
Information systems -- Data management systems
Information systems -- Data management systems -- Database administration
Information systems -- Data management systems -- Database administration -- Data dictionaries
Theory of computation
Theory of computation -- Design and analysis of algorithms
Theory of computation -- Design and analysis of algorithms -- Mathematical optimization
Title A multilevel analytical placement for 3D ICs
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