Experiences in Co-designing a Packet Classification Algorithm and a Flexible Hardware Platform

Algorithmic solutions to the packet classification problem in network equipment have long been a subject of study in academia and industry and with increases in network speeds they are becoming even more important. Since general purpose processors cannot meet performance and cost requirements, resea...

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Bibliographic Details
Published in:2011 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems pp. 189 - 199
Main Authors: Vaish, N., Kooburat, T., De Carli, L., Sankaralingam, K., Estan, C.
Format: Conference Proceeding
Language:English
Published: IEEE 01.10.2011
Subjects:
Arrays
Decision trees
Lookups
Network processing
Packet Classification
Plugs
Program processors
Programming
Random access memory
TCAM
Tiles
ISBN:9781457714542, 145771454X
Online Access:Get full text
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Summary:Algorithmic solutions to the packet classification problem in network equipment have long been a subject of study in academia and industry and with increases in network speeds they are becoming even more important. Since general purpose processors cannot meet performance and cost requirements, researchers have been assuming that ASICs or FPGAs are necessary for hardware implementation. Industry and academia have been working on SRAM-based platforms specialized for tables used in network equipment, but existing publications only describe the mapping of simpler exact match or prefix match lookups to such platforms. In this paper we adopt a software-hardware co-design approach mapping the EffiCuts algorithm to the PLUG platform. Our work confirms that this solution achieves high throughput (142 million packets per second) and low power (3.1 Watts). It identifies and evaluates changes to the original algorithm and to the platform that can improve throughput and memory utilization.
ISBN:9781457714542
145771454X
DOI:10.1109/ANCS.2011.35