A strongly polynomial-time algorithm for over-constraint resolution efficient debugging of timing constraint violations

A system of binary linear constraints or difference constraints (SDC) contains a set of variables that are constrained by a set of unary or binary linear inequalities. In such diverse applications as scheduling, interface timing verification, real-time systems, multimedia systems, layout compaction,...

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Veröffentlicht in:	10th International Symposium on Hardware/Software Codesign S. 127 - 132
1. Verfasser:	Dasdan, Ali
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	New York, NY, USA ACM 06.05.2002 IEEE
Schriftenreihe:	ACM Conferences
Schlagworte:	Compaction Computing methodologies > Artificial intelligence > Knowledge representation and reasoning > Temporal reasoning Debugging High level synthesis Lakes Mathematics of computing > Discrete mathematics > Graph theory > Graph algorithms Mathematics of computing > Mathematical analysis > Nonlinear equations Mathematics of computing > Mathematical analysis > Numerical analysis > Computations on polynomials Multimedia systems Performance gain Permission Polynomials Real time systems Theory of computation > Logic > Modal and temporal logics Timing behavioral synthesis scheduling high-level synthesis constraint satisfaction timing constraints rate analysis
ISBN:	1581135424, 9781581135428
Online-Zugang:	Volltext
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