MAGELLAN multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs

The paper presents MAGELLAN, a heuristic technique for mapping hierarchical control-dataflow task graph specifications on heterogeneous architecture templates. The architecture can consist of multiple hardware and software processing elements as specified by the user. The objective of the technique...

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Vydáno v:	9th International Symposium on Hardware/Software Codesign s. 42 - 47
Hlavní autoři:	Chatha, Karam S., Vemuri, Ranga
Médium:	Konferenční příspěvek
Jazyk:	angličtina
Vydáno:	New York, NY, USA ACM 25.04.2001 IEEE
Edice:	ACM Conferences
Témata:	Communication system control Coprocessors Counting circuits Delay Feedback Partitioning algorithms Pipeline processing Scheduling Software and its engineering > Software creation and management > Designing software Software and its engineering > Software organization and properties > Contextual software domains > Operating systems Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Communications management System buses Timing
ISBN:	1581133642, 9781581133646
On-line přístup:	Získat plný text
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