MAGELLAN multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs

The paper presents MAGELLAN, a heuristic technique for mapping hierarchical control-dataflow task graph specifications on heterogeneous architecture templates. The architecture can consist of multiple hardware and software processing elements as specified by the user. The objective of the technique...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:9th International Symposium on Hardware/Software Codesign S. 42 - 47
Hauptverfasser: Chatha, Karam S., Vemuri, Ranga
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: New York, NY, USA ACM 25.04.2001
IEEE
Schriftenreihe:ACM Conferences
Schlagworte:
Communication system control
Coprocessors
Counting circuits
Delay
Feedback
Partitioning algorithms
Pipeline processing
Scheduling
Software and its engineering > Software creation and management > Designing software
Software and its engineering > Software organization and properties > Contextual software domains > Operating systems
Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Communications management
System buses
Timing
ISBN:1581133642, 9781581133646
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The paper presents MAGELLAN, a heuristic technique for mapping hierarchical control-dataflow task graph specifications on heterogeneous architecture templates. The architecture can consist of multiple hardware and software processing elements as specified by the user. The objective of the technique is to minimize the worst case latency of the task graph subject to the area constraints on the architecture. The technique uses an iterative approach consisting of closely linked hardware-software partitioner and scheduler. Both the partitioner and scheduler operate on the task graph in a hierarchical top down manner. The technique optimizes deterministic loop constructs by applying clustering, unrolling and pipelining. The technique considers speculative execution for conditional constructs. The number of actual hardware/software implementations of a function in the task graph are also optimized by the technique. The effectiveness of the technique is demonstrated by a case study of an image compression algorithm.
Bibliographie:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
content type line 25
ISBN:1581133642
9781581133646
DOI:10.1145/371636.371671