Výsledky vyhledávání - parallel field programmable gate array implementation~

Parallel field programmable gate array implementation of the sum of absolute differences algorithm used in the stereoscopic system Autor Sejai, Mohamed, Mansouri, Anass, Dosse, Saad Bennani, Ruichek, Yassine

“… of the SAD block, and verified by simulation and successfully implemented in Cyclone IV field programmable gate array (FPGA…”
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Field Programmable Gate Array (FPGA) Implementation of Parallel Jacobi for Eigen-Decomposition in Direction of Arrival (DOA) Estimation Algorithm Autor Zhou, Shuang, Zhou, Li

“…) estimation algorithms such as subspace classes. Eigen-decomposition using the parallel Jacobi algorithm implemented on FPGA offers excellent parallelism and real-time performance…”
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Original structure for Walsh–Hadamard transform on sliding window Autor Tisserand, E, Berviller, Y

“… The proposed algorithm requires 2N−2 additions for each projection. The resources used for a parallel field programmable gate array implementation are presented…”
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Toward the Optimal Design and FPGA Implementation of Spiking Neural Networks Autor Guo, Wenzhe, Yantir, Hasan Erdem, Fouda, Mohammed E., Eltawil, Ahmed M., Salama, Khaled Nabil

“… This article proposes a parameter optimization scheme for improving the performance of a biologically plausible SNN and a parallel on-field-programmable gate array (FPGA…”
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FPGA-based implementation of deep neural network using stochastic computing Autor Nobari, Maedeh, Jahanirad, Hadi

“… The reconfigurability and parallel nature of field programmable gate array (FPGA) chips make them a preferable platform for SC-based DNN implementation…”
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Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications Autor Frasser, Christiam F., Linares-Serrano, Pablo, de Rios, Ivan Diez de los, Moran, Alejandro, Skibinsky-Gitlin, Erik S., Font-Rossello, Joan, Canals, Vincent, Roca, Miquel, Serrano-Gotarredona, Teresa, Rossello, Josep L.

“… The proposed architecture solves the challenges that a CNN implementation with SC (SC-CNN) may present, such as the high resources used in binary-to-stochastic conversion…”
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High-dynamic wavelength tracking and millimeter-level ranging inter-satellite laser communication link with feedback-homodyne detection Autor Tian, Yang, Zhong, Jie, Lin, Xiaoxiang, Xiao, Pei, Yang, Haifeng, Zhong, Yu, Kang, Dongpeng

“… In this paper, a system design with a high-sensitivity feedback-homodyne detection scheme and an asynchronous ranging algorithm is demonstrated with real-time field-programmable gate array-implementation (FPGA…”
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Parallel implementations of the fast gradient method for high-speed MPC Autor Peyrl, Helfried, Zanarini, Alessandro, Besselmann, Thomas, Liu, Junyi, Boéchat, Marc-Alexandre

“… In particular, scalable and adaptive implementations of gradient-based optimisation methods are presented for both multi-core CPUs and field programmable gate arrays…”
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Fully-Parallel Stochastic Decoder for Rate Compatible Modulation Autor Lu, Fang, Dong, Yan, Chen, Chang Wen

“… To evaluate the effectiveness of the proposed algorithm, we apply it for the implementation of a field-programmable gate-array fully-parallel stochastic decoder…”
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Parallel Doubly Fed Symbol Timing Recovery Algorithm and FPGA Implementation for Burst Broadband Satellite Access Autor Zhang, Nan, Feng, Jinghan, Zhang, Peixin, Gong, Fengkui

“…) prefilter is also used to improve the algorithm's anti-self-noise capability. The corresponding field programmable gate array (FPGA…”
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Cellular automata implementation of Oregonator simulating light-sensitive Belousov–Zhabotinsky medium Autor Tsompanas, Michail-Antisthenis, Fyrigos, Iosif-Angelos, Ntinas, Vasileios, Adamatzky, Andrew, Sirakoulis, Georgios Ch

“…Cellular automata (CA) have been used to simulate a variety of different chemical, biological and physical phenomena. Their ability to emulate complex…”
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High-Performance Parallel Implementation of Genetic Algorithm on FPGA Autor Torquato, Matheus F., Fernandes, Marcelo A. C.

“… This work proposes a full-parallel implementation of a genetic algorithm on field-programmable gate array (FPGA…”
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The Modular Modulation Chaotification Map and its Hardware Implementation Autor Liu, Wenhao, Sun, Kehui, Wang, Huihai, Li, Binglun

“…The application of chaotic systems is constrained by the prevalence of frail chaos, dynamical degradation, and high costs. To solve these issues, we propose a…”
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Parallel Nonlinear Model Predictive Controller for Real-Time Path Tracking of Autonomous Vehicle Autor Xu, Fang, Zhang, Xu, Chen, Hong, Hu, Yunfeng, Wang, Ping, Qu, Ting

“…), this article presents a parallel NMPC controller based on Newton optimization algorithm and field programmable gate array (FPGA…”
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Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing Autor Li, Limin, Wyrwicz, Alice M

“…) algorithm on a Field Programmable Gate Array (FPGA) for real-time MR image processing. Although a number of architectures of 2D FFT hardware processors…”
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Hybrid analytical model of switched reluctance machine for real-time hardware-in-the-loop simulation Autor Xu, Fengqiu, Dinavahi, Venkata, Xu, Xianze

“… The digital hardware implementation of computation components are developed on the field-programmable gate…”
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Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs Autor Gang Zhou, Michalik, Harald, Hinsenkamp, László

“…) and on field-programmable gate arrays (FPGAs)] and efficient FPGA implementations of bit parallel mixed Karatsuba-Ofman multipliers (KOM) over GF(2 m…”
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Parallel design of intelligent optimization algorithm based on FPGA Autor Zou, Xiaofu, Wang, Lina, Tang, Yue, Liu, Yilong, Zhan, Shicheng, Tao, Fei

“…) and compute unified device architecture (CUDA) are two popular methods. To find and develop a new IOA parallel method, in this paper, a parallel design and implementation method based on field programmable gate array (FPGA) is explored…”
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FPGA-based hardware implementation of chaotic opposition-based arithmetic optimization algorithm Autor Zermani, Mohamed Aymen, Manita, Ghaith, Chhabra, Amit, Feki, Elyes, Mami, Abdelkader

“… Our proposed hardware implementation of COAOA harnesses Field-Programmable Gate Arrays (FPGAs) to accelerate optimization processes…”
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FPGA-Based Distributed Union-Find Decoder for Surface Codes Autor Liyanage, Namitha, Wu, Yue, Tagare, Siona, Zhong, Lin

“… Using a field-programmable gate array (FPGA)-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity…”
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