Search Results - parallel field programmable game array implementation
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A Highly-Parallel and Scalable Hardware Accelerator for the NTest Othello Game Engine
ISSN: 1045-9219, 1558-2183Published: IEEE 01.08.2025Published in IEEE transactions on parallel and distributed systems (01.08.2025)“… We describe its architecture and Field Programmable Gate Array implementation, measure its performance, and compare it with prior solutions…”
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Journal Article -
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Hardware Architectures for Real-Time Medical Imaging
ISSN: 2079-9292, 2079-9292Published: Basel MDPI AG 01.12.2021Published in Electronics (Basel) (01.12.2021)“…Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of…”
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Energy Efficient Parallel and Distributed Simulation
ISBN: 9798263374204Published: ProQuest Dissertations & Theses 01.01.2019“… In mobile systems energy consumption directly impacts battery life. This work focuses on understanding and minimizing power and energy consumption in parallel…”
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Dissertation -
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The acceleration of 3D graphics transformations based on CUDA
ISSN: 1726-0531, 1758-8901Published: Bingley Emerald Group Publishing Limited 04.12.2018Published in Journal of engineering, design and technology (04.12.2018)“…PurposeThe purpose of this paper is to achieve the acceleration of 3D object transformation using parallel techniques such as multi-core central processing unit (MC CPU…”
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Journal Article -
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A Case Study: Undergraduate Self-Learning in HPC Including OpenMP, MPI, OpenCL, and FPGAs
Published: IEEE 01.12.2019Published in 2019 International Conference on Computational Science and Computational Intelligence (CSCI) (01.12.2019)“…High Performance Computing (HPC) continues to develop and encroach on higher-education in the computing fields…”
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Conference Proceeding -
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Accelerating Deep Neuroevolution on Distributed FPGAs for Reinforcement Learning Problems
ISSN: 2331-8422Published: Ithaca Cornell University Library, arXiv.org 10.05.2020Published in arXiv.org (10.05.2020)“… Combined hardware implementation of the game console, image pre-processing and the neural network in an optimized pipeline, multiplied with the system level parallelism enabled the acceleration…”
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Paper -
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Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform
Published: IEEE 01.12.2017Published in ReConFig '17 : 2017 International Conference on Reconfigurable Computing and FPGAs : Cancun, Mexico, December 4-6, 2017 (01.12.2017)“… These types of algorithms are, typically, critical real-time calculations needed for applications such as simulation, tolerance checking, and video games…”
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Conference Proceeding -
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Development of Filled Circle Drawing in High-Level Synthesis Oriented Game Programming Library
ISSN: 2640-6721Published: IEEE 01.12.2019Published in 2019 20th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT) (01.12.2019)“…We are developing a high-level synthesizable software game library to realize high performance and low power mobile terminals executing game applications…”
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Conference Proceeding -
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Reconfigurable implementation of elliptic curve crypto algorithms
ISBN: 9780769515731, 0769515738Published: IEEE 2002Published in Proceedings: International Parallel and Distributed Processing Symposium: April 15-19, 2002, Ft. Lauderdale, Florida, USA (2002)Get full text
Conference Proceeding -
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An FPGA implementation of 3D affine transformations
ISBN: 0780381637, 9780780381636Published: IEEE 2003Published in ICECS 2003 : proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits, and Systems : December 14-17, 2003, Sharjah, United Arab Emirates (2003)“…) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA…”
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Conference Proceeding -
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Solving Sudoku in reconfigurable hardware
ISBN: 1467313262, 9781467313261Published: IEEE 01.08.2012Published in ICCNT 2012 : proceedings : 2012 8th International Conference on Computing and Networking Technology (INC, ICCIS and ICMIC) : Gyeongju Hilton Hotel, Gueongju, Korea (Republic of), August 27-28, 2012 (01.08.2012)“… (Field-Programmable Gate Array) on an example of Sudoku game. Three different Sudoku solvers have been fully implemented and tested on a low-cost FPGA of Xilinx Spartan-3E family…”
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Conference Proceeding -
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A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices
ISSN: 2325-6532Published: IEEE 01.12.2013Published in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (01.12.2013)“… The whole practice turns into a skill game that heavily depends on the personal skills and experience of the programmer…”
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Conference Proceeding -
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Towards Comparing Performance of Algorithms in Hardware and Software
ISSN: 2331-8422Published: Ithaca Cornell University Library, arXiv.org 25.05.2022Published in arXiv.org (25.05.2022)“…In this paper, we report on a preliminary investigation of the potential performance gain of programs implemented in field-programmable gate arrays (FPGAs…”
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Paper -
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Modeling memory resources distribution on multicore processors using games on cellular automata lattices
ISBN: 9781424465330, 1424465338Published: IEEE 01.04.2010Published in 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (01.04.2010)“… The proposed model uses the basic concepts of game theory applied to cellular automata lattices and the iterated spatial prisoner's dilemma game…”
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Conference Proceeding -
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Parallel Brutus: the first distributed, FPGA accelerated chess program
ISBN: 0769521320, 9780769521329Published: IEEE 2004Published in Parallel and Distributed Processing: Proceedings, 18th International Symposium, Santa Fe, NM, 2004 (2004)“… It is now possible to develop fine grained parallel applications without long-lasting chip design cycles…”
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Conference Proceeding -
16
Acceleration of Multi-agent Simulation on FPGAs
ISBN: 9781457714849, 1457714841ISSN: 1946-147XPublished: IEEE 01.09.2011Published in 2011 21st International Conference on Field Programmable Logic and Applications (01.09.2011)“… In this paper, we propose an FPGA-based framework for massive-scale grid-based MAS. Memory interleaving, parallel tasks partition, and computing pipeline are adopted to improve system throughput…”
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Conference Proceeding -
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Population-Based FPGA Solution to Mastermind Game
ISBN: 0769526144, 9780769526140Published: IEEE 2006Published in First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006): 15-18 June 2006/Istanbul, Turkey (2006)“…We present a new parallel, adaptable algorithm, which plays Mastermind game, and its FPGA implementation…”
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Conference Proceeding

