Search Results - parallel field programmable game array implementation

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  1. 1

    A Highly-Parallel and Scalable Hardware Accelerator for the NTest Othello Game Engine by Popa, Stefan, Petric, Vlad, Ivanovici, Mihai

    ISSN: 1045-9219, 1558-2183
    Published: IEEE 01.08.2025
    “… We describe its architecture and Field Programmable Gate Array implementation, measure its performance, and compare it with prior solutions…”
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    Journal Article
  2. 2

    Hardware Architectures for Real-Time Medical Imaging by Alcaín, Eduardo, Fernández, Pedro R., Nieto, Rubén, Montemayor, Antonio S., Vilas, Jaime, Galiana-Bordera, Adrian, Martinez-Girones, Pedro Miguel, Prieto-de-la-Lastra, Carmen, Rodriguez-Vila, Borja, Bonet, Marina, Rodriguez-Sanchez, Cristina, Yahyaoui, Imene, Malpica, Norberto, Borromeo, Susana, Machado, Felipe, Torrado-Carvajal, Angel

    ISSN: 2079-9292, 2079-9292
    Published: Basel MDPI AG 01.12.2021
    Published in Electronics (Basel) (01.12.2021)
    “…Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of…”
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    Journal Article
  3. 3

    Energy Efficient Parallel and Distributed Simulation by Biswas, Aradhya

    ISBN: 9798263374204
    Published: ProQuest Dissertations & Theses 01.01.2019
    “… In mobile systems energy consumption directly impacts battery life. This work focuses on understanding and minimizing power and energy consumption in parallel…”
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    Dissertation
  4. 4

    The acceleration of 3D graphics transformations based on CUDA by Sura Nawfal, Fakhrulddin Ali

    ISSN: 1726-0531, 1758-8901
    Published: Bingley Emerald Group Publishing Limited 04.12.2018
    “…PurposeThe purpose of this paper is to achieve the acceleration of 3D object transformation using parallel techniques such as multi-core central processing unit (MC CPU…”
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    Journal Article
  5. 5

    A Case Study: Undergraduate Self-Learning in HPC Including OpenMP, MPI, OpenCL, and FPGAs by Jamieson, Peter, Herbordt, Martin, Kinsy, Michel

    Published: IEEE 01.12.2019
    “…High Performance Computing (HPC) continues to develop and encroach on higher-education in the computing fields…”
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    Conference Proceeding
  6. 6

    Accelerating Deep Neuroevolution on Distributed FPGAs for Reinforcement Learning Problems by Asseman, Alexis, Antoine, Nicolas, Ozcan, Ahmet S

    ISSN: 2331-8422
    Published: Ithaca Cornell University Library, arXiv.org 10.05.2020
    Published in arXiv.org (10.05.2020)
    “… Combined hardware implementation of the game console, image pre-processing and the neural network in an optimized pipeline, multiplied with the system level parallelism enabled the acceleration…”
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    Paper
  7. 7

    Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform by Alves, Fredy Augusto M., Jamieson, Peter, da Silva, Lucas B., Ferreira, Ricardo S., Nacif, Jose Augusto M.

    Published: IEEE 01.12.2017
    “… These types of algorithms are, typically, critical real-time calculations needed for applications such as simulation, tolerance checking, and video games…”
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    Conference Proceeding
  8. 8

    Development of Filled Circle Drawing in High-Level Synthesis Oriented Game Programming Library by Yamagata, Yuki, Yamawaki, Akira

    ISSN: 2640-6721
    Published: IEEE 01.12.2019
    “…We are developing a high-level synthesizable software game library to realize high performance and low power mobile terminals executing game applications…”
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    Conference Proceeding
  9. 9
  10. 10

    An FPGA implementation of 3D affine transformations by Bensaali, F., Amira, A., Uzun, I.S., Ahmedsaid, A.

    ISBN: 0780381637, 9780780381636
    Published: IEEE 2003
    “…) or visualization applications. This paper investigates the suitability of Field Programmable Gate Array (FPGA…”
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    Conference Proceeding
  11. 11

    Solving Sudoku in reconfigurable hardware by Skliarova, I., Vallejo, T., Sklyarov, V.

    ISBN: 1467313262, 9781467313261
    Published: IEEE 01.08.2012
    “… (Field-Programmable Gate Array) on an example of Sudoku game. Three different Sudoku solvers have been fully implemented and tested on a low-cost FPGA of Xilinx Spartan-3E family…”
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    Conference Proceeding
  12. 12

    A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices by Kavun, Elif Bilge, Leander, Gregor, Yalcind, Tolga

    ISSN: 2325-6532
    Published: IEEE 01.12.2013
    “… The whole practice turns into a skill game that heavily depends on the personal skills and experience of the programmer…”
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    Conference Proceeding
  13. 13

    Towards Comparing Performance of Algorithms in Hardware and Software by Kirkeby, Maja H, Schoeberl, Martin

    ISSN: 2331-8422
    Published: Ithaca Cornell University Library, arXiv.org 25.05.2022
    Published in arXiv.org (25.05.2022)
    “…In this paper, we report on a preliminary investigation of the potential performance gain of programs implemented in field-programmable gate arrays (FPGAs…”
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    Paper
  14. 14

    Modeling memory resources distribution on multicore processors using games on cellular automata lattices by Tsompanas, Michail-Antisthenis I, Sirakoulis, Georgios Ch, Karafyllidis, Ioannis

    ISBN: 9781424465330, 1424465338
    Published: IEEE 01.04.2010
    “… The proposed model uses the basic concepts of game theory applied to cellular automata lattices and the iterated spatial prisoner's dilemma game…”
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    Conference Proceeding
  15. 15

    Parallel Brutus: the first distributed, FPGA accelerated chess program by Donninger, C., Kure, A., Lorenz, U.

    ISBN: 0769521320, 9780769521329
    Published: IEEE 2004
    “… It is now possible to develop fine grained parallel applications without long-lasting chip design cycles…”
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    Conference Proceeding
  16. 16

    Acceleration of Multi-agent Simulation on FPGAs by Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He

    ISBN: 9781457714849, 1457714841
    ISSN: 1946-147X
    Published: IEEE 01.09.2011
    “… In this paper, we propose an FPGA-based framework for massive-scale grid-based MAS. Memory interleaving, parallel tasks partition, and computing pipeline are adopted to improve system throughput…”
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    Conference Proceeding
  17. 17

    Population-Based FPGA Solution to Mastermind Game by Ugurdag, H.F., Sahin, Y., Baskirt, O., Dedeoglu, S., Goren, S., Kocak, Y.S.

    ISBN: 0769526144, 9780769526140
    Published: IEEE 2006
    “…We present a new parallel, adaptable algorithm, which plays Mastermind game, and its FPGA implementation…”
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    Conference Proceeding