Search Results - field-programmable gate array (fpga) (implementations OR implementation)

Implementation of data cache block (DCB) in shared processor using field-programmable gate array (FPGA) by Karthick, R, Meenalochini, P

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Weighted p -Bits for FPGA Implementation of Probabilistic Circuits by Pervaiz, Ahmed Zeeshan, Sutton, Brian M., Ghantasala, Lakshmi Anirudh, Camsari, Kerem Y.

“… to find the input combinations that are consistent with a given output. In this brief, we present a scalable field-programmable gate array implementation of such invertible p-circuits…”
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Sine-Transform-Based Chaotic System With FPGA Implementation by Hua, Zhongyun, Zhou, Binghang, Zhou, Yicong

“…As chaotic dynamics is widely used in nonlinear control, synchronization communication, and many other applications, designing chaotic maps with complex…”
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Memristor-induced hyperchaos, multiscroll and extreme multistability in fractional-order HNN: Image encryption and FPGA implementation by Kong, Xinxin, Yu, Fei, Yao, Wei, Cai, Shuo, Zhang, Jin, Lin, Hairong

“…Fractional-order differentiation (FOD) can record information from the past, present, and future. Compared with integer-order systems, FOD systems have higher…”
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Novel optimized implementations for the Piccolo cipher based on field‐programmable gate arrays by Feng, Jingya, Wei, Yongzhuang, Wei, Bohua

“…In the era of the highly pervasive Internet of Things (IoT), the optimized implementation of lightweight cryptographic algorithms for protecting data security has extensively received attention, for instance, the Piccolo cipher…”
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A Fast and Adaptive Dynamic Phasor Estimation Algorithm Implemented on Field Programmable Gate Array (FPGA) by Samantaray, Subhransu Ranjan, Nanda, Sarita, Dash, P.K.

“…A fast and precise dynamic phasor estimation algorithm using an adaptive improved second order Levenberg-Marquadt algorithm under stressed and off-nominal…”
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Field Programmable Gate Array (FPGA) Implementation of Parallel Jacobi for Eigen-Decomposition in Direction of Arrival (DOA) Estimation Algorithm by Zhou, Shuang, Zhou, Li

“…) estimation algorithms such as subspace classes. Eigen-decomposition using the parallel Jacobi algorithm implemented on FPGA offers excellent parallelism and real-time performance…”
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High-Speed and Low-Latency ECC Processor Implementation Over GF( 2^) on FPGA by Khan, Zia U. A., Benaissa, Mohammed

“…) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery…”
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An Energy-Efficient Field-Programmable Gate Array (FPGA) Implementation of a Real-Time Perspective-n-Point Solver by Lv, Haobo, Wu, Qiongzhi

“… To handle this challenge, we present an originally designed FPGA implementation of a PnP solver based on Vivado HLS…”
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Speed/Area-Efficient ECC Processor Implementation Over GF(2 ^m) on FPGA via Novel Algorithm-Architecture Co-Design by Zeghid, Medien, Ahmed, Hassan Yousif, Chehri, Abdellah, Sghaier, Anissa

“…) processor implementation on the field-programmable gate array (FPGA) platform, we have proposed a bottom-up approach based on three coherent interdependent layers of efforts…”
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Dynamics analysis, synchronization and FPGA implementation of multiscroll Hopfield neural networks with non-polynomial memristor by Yu, Fei, Kong, Xinxin, Yao, Wei, Zhang, Jin, Cai, Shuo, Lin, Hairong, Jin, Jie

“…) is typically coupled with the number of polynomials, which leads to a coupling between the computational complexity and resource utilization in circuit implementation…”
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Design and Verification of Petri-Net-Based Cyber-Physical Systems Oriented toward Implementation in Field-Programmable Gate Arrays—A Case Study Example by Wiśniewski, Remigiusz, Wojnakowski, Marcin, Li, Zhiwu

“…). The idea is oriented toward implementation in a field-programmable gate array (FPGA). The proposed technique permits error detection in the system at the early specification stage in order to reduce the time and prototyping cost of the CPS…”
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Logic Neural Networks for Efficient FPGA Implementation by Ramirez, Ivan, Garcia-Espinosa, Francisco J., Concha, David, Aranda, Luis Alberto

“…Logic Neural Networks (LNNs) represent a new paradigm for implementing neural networks in hardware devices such as Field-Programmable Gate Arrays (FPGAs…”
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Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform by Majoral, Marc, Arribas, Javier, Fernández-Prades, Carles

“… Leveraging System-on-Chip Field-Programmable Gate Array (SoC-FPGA) technology, this design merges the adaptability of Software Defined Radio (SDR…”
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A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection by Nguyen, Duy Thanh, Nguyen, Tuan Nghia, Kim, Hyun, Lee, Hyuk-Jae

“… The binary weight enables storing the entire network model in block RAMs of a field-programmable gate array (FPGA…”
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A new 4‐D hyperchaotic two‐scroll system with hidden attractor and its field‐programmable gate array implementation by Vaidyanathan, Sundarapandian, Benkouider, Khaled, Ovilla‐Martinez, Brisbane, Tlelo‐Cuautle, Esteban, Sambas, Aceng, Darwin, P.

“…‐scroll system with hidden attractor is prototyped using the field‐programmable gate array (FPGA) Zybo Z7…”
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Toward the Optimal Design and FPGA Implementation of Spiking Neural Networks by Guo, Wenzhe, Yantir, Hasan Erdem, Fouda, Mohammed E., Eltawil, Ahmed M., Salama, Khaled Nabil

“… This article proposes a parameter optimization scheme for improving the performance of a biologically plausible SNN and a parallel on-field-programmable gate array (FPGA…”
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Standoff Tracking Using DNN-Based MPC With Implementation on FPGA by Dong, Fei, Li, Xingchen, You, Keyou, Song, Shiji

“…) simulation with a field-programmable gate array (FPGA) at <inline-formula> <tex-math notation="LaTeX">200</tex-math> </inline-formula> MHz demonstrates that our method…”
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Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation by Gholami, Morteza, Zaman Farsa, Edris, Karimi, Gholamreza

“…Summary Hardware implementations of spiking neural networks, which are known as neuromorphic architectures, provide an explicit understanding of brain performance…”
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Enhanced Interpolated-DFT for Synchrophasor Estimation in FPGAs: Theory, Implementation, and Validation of a PMU Prototype by Romano, Paolo, Paolone, Mario

“…; the assessment of the influence of the e-IpDFT parameters on the SE accuracy; and the discussion of the deployment of IpDFT-based SE algorithms into field programmable gate…”
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