Výsledky vyhledávání - field-programmable game array implementations

Radar-Jamming Decision-Making Based on Improved Q-Learning and FPGA Hardware Implementation Autor Zheng, Shujian, Zhang, Chudi, Hu, Jun, Xu, Shiyou

“… At the same time, we performed a comprehensive design and implementation based on the classical…”
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A Highly-Parallel and Scalable Hardware Accelerator for the NTest Othello Game Engine Autor Popa, Stefan, Petric, Vlad, Ivanovici, Mihai

“… We describe its architecture and Field Programmable Gate Array implementation, measure its performance, and compare it with prior solutions…”
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ZX Fusion: A ZX Spectrum Implementation on an FPGA with Modern Peripherals Autor Jacinto, Gustavo, Policarpo Duarte, Rui

“… while being compatible with existing software. This implementation is a means by which to validate the methodology before applying it to a…”
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Physical education image analysis based on virtual crowd simulation and FPGA Autor Leilei, Wang, Huina, Cheng

“…Physical Culture and Sports research are coordinated with the game (rational, educators, game director, and game theory from a specific or a general point) medicine sociology…”
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Hardware Architectures for Real-Time Medical Imaging Autor Alcaín, Eduardo, Fernández, Pedro R., Nieto, Rubén, Montemayor, Antonio S., Vilas, Jaime, Galiana-Bordera, Adrian, Martinez-Girones, Pedro Miguel, Prieto-de-la-Lastra, Carmen, Rodriguez-Vila, Borja, Bonet, Marina, Rodriguez-Sanchez, Cristina, Yahyaoui, Imene, Malpica, Norberto, Borromeo, Susana, Machado, Felipe, Torrado-Carvajal, Angel

“…Medical imaging is considered one of the most important advances in the history of medicine and has become an essential part of the diagnosis and treatment of…”
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FPGA-based Accelerator for AI-Toolbox Reinforcement Learning Library Autor Leiva, Lucas, Torrents-Barrena, Jordina, Vazquez, Martin

“… RL methodologies require processing large volumes of data and computational power. To speed up these applications, field-programmable gate array (FPGA…”
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Decay-Based DRAM PUFs in Commodity Devices Autor Schaller, Andre, Xiong, Wenjie, Anagnostopoulos, Nikolaos Athanasios, Saleem, Muhammad Umair, Gabmeyer, Sebastian, Skoric, Boris, Katzenbeisser, Stefan, Szefer, Jakub

“… So far, most PUF constructions have required an addition of new hardware or an FPGA implementation for their operation…”
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Human tracking of track and field athletes based on FPGA and computer vision Autor Jiang, Xin

“… This article aims to accelerate image recognition and object tracking; propose a one-dimensional data pipeline architecture on a Field-Programmable Gate Array (FPGA…”
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An FPGA Integrated 2D Graphic Processor for Enhanced Digital Design and Computer Architecture Education Autor Sa Alves, Gabriel B., Carlos Bittencourt, Joao N., Dias, Anfranserai

“… Consequently, the adoption of Field Programmable Gate Array (FPGA) co-design approaches, which integrate hardware and software aspects of systems, represents…”
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Optimized Attention with Sparse Graph Convolutional Network Based Tumor Segmentation Using Field Programmable Gated Array Autor V, Vaithianathan, Nagarani, S., Rajalakshmi, R., D, Shyamprakash, Aparna, G., Rajavelu, S.

“… In this study, a field programmable gate array (FPGA) for BT segmentation using optimized Residual group attention network based Sparse Graph Convolutional Neural Network (RGAN-SGCNN) is introduced…”
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A Strategical Approach for Implementing Digital Games on FPGA Autor Ali, Sk Irfan, Shyam, P, Dilkush, Sk, Baby, M, Kalyani, P, Suresh, S, Teja, G, Jayasri, S

“…Field Programmable Gate Arrays (FPGAs) are providing potential solutions to the most of the technological advancements…”
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Design and Implementation of Galaxian Game Based on FPGA Architecture Autor Xu, Xiao Le, Ding, Guo Dong, Liu, Chang Hua

“… more fast. At the same time, the need in the entertainment is also growing. The game based on handheld is becoming more and more…”
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FPGA implementation of trellis decoders for linear block codes Autor Scholl, S., Leonardi, E., Wehn, N.

“… In this paper we present for the first time hardware architectures and implementations for trellis decoding of block codes…”
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AlphaGo Policy Network: A DCNN Accelerator on FPGA Autor Li, Zhenni, Zhu, Can, Gao, Yu-Liang, Wang, Ze-Kun, Wang, Jiao

“…The game of GO has long been regarded as the most challenging game for artificial intelligence because of its enormous search space and the difficulty of evaluating its board positions…”
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High-Performance Image Acquisition and Processing for Stereoscopic Diagnostic Systems with the Application of Graphical Processing Units Autor Perek, Piotr, Mielczarek, Aleksander, Makowski, Dariusz

“… The creators of movies, games, and augmented reality applications are aware of this technology’s advantages, possibilities, and new means of expression…”
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Simplified Design of an FPGA-Accelerated Connectionless Network Stack Autor Sferle, Alin-Tudor, Blaga, Tudor-Mihai, Zinca, Daniel, Dobrota, Virgil

“… The Field-Programmable Gate Array (FPGA) is the most chosen hardware solution for such an implementation…”
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Hardware Implementation of Spherical Diffuse Reflection in Ray-Casting Using High Level-Synthesis Autor Kurata, Kazuki, Yamawaki, Akira

“…Game applications require high graphics, and it is not suitable for mobile devices which is battery-powered because of heavy processing load…”
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FPGA implementation of multiple Pursuit-Evasion games with decentralized Learning Automata Autor Gao, Shuli, Givigi, Sidney N., Beaulieu, Alain Jg

“…This paper addresses the implementation of multiple Pursuit-Evasion (PE) games using Field Programmable Gate Array (FPGA) technology…”
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Hardware/Software Co-Design of a High-Speed Othello Solver Autor Gangwar, Pranav, Maurya, Satvik, Garg, Shubham, Goyal, Sakshi, Kumar, Aditya S, Dalmia, Preyesh, Pandey, Neeta

“…This paper presents an improved Othello game solver using the Hardware/Software Co-Design approach…”
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Design and Implementation of Cellular Automata on FPGA for Hardware Acceleration Autor Bakhteri, Rabia, Cheng, Julian, Semmelhack, Alex

“… In this paper, we proposed and implemented the CA called Conway’s Game of Life (CGoL) on a Field-Programmable Gate Array (FPGA…”
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