Suchergebnisse - combinational-circuit decoding complexity

Two reliability-based iterative majority-logic decoding algorithms for LDPC codes von Huang, Q, Kang, J, Zhang, L, Lin, S, Abdel-Ghaffar, K

“… of decoding convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance …”
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Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications von Kazeminejad, A

“… A fast, minimal decoding complexity, binary systematic single-error-correcting code with one extra parity-bit penalty is presented …”
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An Improved Majority-Logic Decoder Offering Massively Parallel Decoding for Real-Time Control in Embedded Systems von Bertram, Juliane, Hauck, Peter, Huber, Michael

“… A simple combinational circuit can perform the proposed decoding. In particular, we show how our decoder for the three-error-correcting code RM(2, 5 …”
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Joint detection–decoding of majority-logic decodable non-binary low-density parity-check coded modulation systems: an iterative noise reduction algorithm von Zhao, Shancheng, Wang, Xuepeng, Wang, Teng, Bai, Baoming, Ma, Xiao

“… In this study, the authors present a low-complexity iterative joint detection–decoding algorithm for majority-logic decodable non-binary low-density parity-check (LDPC …”
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Efficient Error Correcting Codes for On-Chip DRAM Applications for Space Missions von Baloch, S., Arslan, T., Stoica, A.

“… These new, codes-based circuits can be used in combinational circuits and in on-chip random access memories of reconfigurable architectures with high performance and ultimate minimum decoding/encoding complexity …”
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Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications von Kazeminejad, A

“… Fast, minimal decoding complexity (13, 8) binary systematic single-error-correcting codes are proposed for on-chip DRAM applications. These (13, 8 …”
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High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits von Jaber, Ramzi A., Kassem, Abdallah, El-Hajj, Ahmad M., El-Nimri, Lina A., Haidar, Ali Massoud

“… )] and combinational circuits [ternary decoder (TDecoder), ternary half-adder (THA), and ternary multiplier (TMUL …”
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Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications von Amir, K., Eric, B.

“… Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications are presented. These (41, 32 …”
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Novel method of designing all optical frequency-encoded Fredkin and Toffoli logic gates using semiconductor optical amplifiers von Garai, S.K.

“… Reversible logic gates have attracted significant attention to researchers in the field of optics and optoelectronics because of its wide applications in sequential and combinational circuit …”
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Two efficient and low-complexity iterative reliability-based majority-logic decoding algorithms for LDPC codes von Qin Huang, Jingyu Kang, Li Zhang, Shu Lin, Abdel-Ghaffar, K.

“… convergence and less decoding complexity. Compared to the sum-product algorithm for LDPC codes, they offer effective trade-offs between performance and decoding complexity …”
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Computational complexity of controllability/observability problems for combinational circuits von Fujiwara, H.

“… The computational complexity of fault detection problems and various controllability and observability problems for combinational logic circuits are analyzed …”
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Customized Algorithms for High Performance Memory Test in Advanced Technology Node von Shomo Chen, Ning Huang, Ting-Pu Tai, Niu, A.

“… This paper describes how ASIC vendors can develop customized memory test algorithms to enhance their overall IC testing strategy. BIST test algorithm was used …”
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Early outpoint insertion for high-level software vs. RTL formal combinational equivalence verification von Xiushan Feng, Hu, A.J.

“… Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intended for synthesis …”
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Complexity of decoders--I: Classes of decoding rules von Savage, J.

“… Under the assumption that these rules are implemented with combinational circuits and sequential machines constructed with AND gates, OR gates, INVERTERS, and binary memory cells, bounds are derived on their complexity …”
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