Search Results - booth encoding algorithm

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  1. 1

    Implementation of efficient MAC for DSP applications using Modified Booth Encoding algorithm technique by Tamilselvan, S, Dharani, S, Ramesh, R, HemaPriya, K

    ISSN: 1757-8981, 1757-899X
    Published: Bristol IOP Publishing 01.03.2021
    “… A modified booth Encoding (MBE) multiplier is used to execute a multiplier in floating point multiplier in order to significantly reduce partial products into half…”
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    Journal Article
  2. 2

    SPEED ENHANCEMENT OF MODIFIED BOOTHS ENCODING ALGORITHM USING VERILOG HDL by GOPI, CHAND NAGUBOINA, SRAVYA, T.

    ISSN: 2321-7480, 2322-0368
    Published: Nagercoil iManager Publications 2019
    “…This paper presents the design and implementation of Modified Booths encoding algorithm with enhanced speed…”
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    Journal Article
  3. 3

    Design of Radix-8 Unsigned Bit Pair Recoding Algorithm-Based Floating-Point Multiplier for Neural Network Computations by Nesam, J. Jean Jenifer, Ganesh, S. Sankar

    ISSN: 2169-3536, 2169-3536
    Published: Piscataway IEEE 2025
    Published in IEEE access (2025)
    “… The new algorithm performs partial product row reduction without the 2's complement, Negative Encoding (NE…”
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    Journal Article
  4. 4

    A New Redundant Binary Booth Encoding for Fast 2^-Bit Multiplier Design by Yajuan He, Chip-Hong Chang

    ISSN: 1549-8328, 1558-0806
    Published: IEEE 01.06.2009
    “… To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired…”
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    Journal Article
  5. 5

    Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers by Muralidharan, Ramya, Chang, Chip-Hong

    ISSN: 1549-8328, 1558-0806
    Published: New York IEEE 01.11.2013
    “… The former employs the radix- 2^{2} Booth encoding algorithm and the latter employs the radix- 2^{3…”
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    Journal Article
  6. 6

    Two Speed Modified Radix-4 Booth Multiplier With Different Adder Configurations by Reshma, V P, Adersh, V R

    Published: IEEE 21.10.2021
    “…In this proposed system, a two speed modified radix-4 booth multiplier algorithm with different adder configurations are implemented for the applications like digital signal processing, digital…”
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    Conference Proceeding
  7. 7

    Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications by Gundavarapu, Vishal, Gowtham, P., Anita Angeline, A., Sasipriya, P.

    ISSN: 0141-9331, 1872-9436
    Published: Elsevier B.V 01.04.2024
    Published in Microprocessors and microsystems (01.04.2024)
    “… In this paper, 8-bit approximate Booth multipliers have been proposed based on the approximate Radix-4 modified Booth encoding algorithm and approximate compressors for partial product accumulation…”
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    Journal Article
  8. 8

    Design and Analysis of Area and Power Efficient Approximate Booth Multipliers by Venkatachalam, Suganthi, Adams, Elizabeth, Lee, Hyuk Jae, Ko, Seok-Bum

    ISSN: 0018-9340, 1557-9956
    Published: New York IEEE 01.11.2019
    Published in IEEE transactions on computers (01.11.2019)
    “… Radix-4 modified Booth encoding is a popular multiplication algorithm which reduces the size of the partial product array by half…”
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    Journal Article
  9. 9

    High Energy Efficiency Radix-4 Booth Multiplier with Zero Encoding Skipping Mechanism by Zhu, Xinyu, Li, Hongge, Song, Yinjie, Chen, Yuhao, Guo, Xiaoyu

    ISSN: 2159-3477
    Published: IEEE 01.07.2024
    “… The method can convert non-zero encoding to zero encoding of the radix-4 Booth algorithm, which increases the number of zero encodings and thus reduces the number of multiplication operations…”
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    Conference Proceeding
  10. 10

    Exact and approximate Radix-4 recoding multipliers for high-efficiency computation by Zhu, Xinyu, Li, Hongge, Song, Yinjie

    ISSN: 1879-2391
    Published: Elsevier Ltd 01.03.2025
    Published in Microelectronics (01.03.2025)
    “… The proposed encoding methods realize the transformation from non-zero to zero encodings of the radix-4 Booth algorithm, which increases the number of zero encodings…”
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    Journal Article
  11. 11

    A New Redundant Binary Partial Product Generator for Fast 2n-Bit Multiplier Design by Cui Xiaoping, Hu Wei, Chen Xin, Wang Shumin

    Published: IEEE 01.12.2014
    “…The radix-4 Booth encoding or Modified Booth encoding (MBE) has been widely adopted in partial products generator to design high-speed redundant binary (RB) multipliers…”
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    Conference Proceeding
  12. 12

    Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing by Liu, Weiqiang, Qian, Liangyu, Wang, Chenghua, Jiang, Honglan, Han, Jie, Lombardi, Fabrizio

    ISSN: 0018-9340, 1557-9956
    Published: New York IEEE 01.08.2017
    Published in IEEE transactions on computers (01.08.2017)
    “…) and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on approximate radix-4 modified Booth encoding (MBE…”
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    Journal Article
  13. 13

    High Accuracy Fixed Width Multipliers using Modified Booth Algorithm by Kumar, R. Vignesh, Kamala, J.

    ISSN: 1877-7058, 1877-7058
    Published: Elsevier Ltd 2012
    Published in Procedia engineering (2012)
    “…In this paper, using Radix-4 Modified Booth Encoding (MBE) algorithm high accuracy fixed width multiplier is developed…”
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    Journal Article
  14. 14

    An Efficient Approximate Radix-8 Booth Multiplier for Edge Detection in Bioimages by Field Programmable Gate Array by Esmaeili, Elham, Ranjbar, Ali, Rafiei, Shabnam, Shiri, Nabiollah

    ISSN: 1549-8328, 1558-0806
    Published: IEEE 01.01.2025
    “…The Booth multiplier provides high-performance signed multiplication by encoding and decreasing partial products (PPs…”
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    Journal Article
  15. 15

    A New Redundant Binary Booth Encoding for Fast 2 n -Bit Multiplier Design by He, Yajuan, Chang, Chip-Hong

    ISSN: 1549-8328
    Published: 01.01.2009
    “… To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired…”
    Get full text
    Journal Article
  16. 16

    A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier by Cheng, Quan, Dai, Liuyao, Huang, Mingqiang, Shen, Ao, Mao, Wei, Hashimoto, Masanori, Yu, Hao

    ISSN: 1549-7747, 1558-3791
    Published: New York IEEE 01.06.2023
    “… The accelerator includes a radix-4 Booth multiplier for pre-encoding weights to reduce the number of partial products (PPs…”
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    Journal Article
  17. 17

    A New Redundant Binary Booth Encoding for Fast2{n}-Bit Multiplier Design by He, Y., Chang, C.-H.

    ISSN: 1549-8328
    Published: 01.06.2009
    “… To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired…”
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    Journal Article
  18. 18

    Design and optimization of a quaternary booth multiplier in quaternary logic using carbon nanotube transistors by toosanloo, Sobhan Aghamalizadeh, javidan, javad

    ISSN: 2045-2322, 2045-2322
    Published: London Nature Publishing Group UK 14.10.2025
    Published in Scientific reports (14.10.2025)
    “…Employing the Booth algorithm to generate partial products and utilizing the Wallace tree method for compressing these products significantly enhance the speed of multipliers…”
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    Journal Article
  19. 19
  20. 20

    Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier by Jain, Riya, Pahwa, Khushbu, Pandey, Neeta

    ISSN: 1336-1376, 1804-3119
    Published: Ostrava Faculty of Electrical Engineering and Computer Science VSB - Technical University of Ostrava 01.09.2021
    “… In this paper, we propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier…”
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    Journal Article