Výsledky vyhledávání - algorithms implemented in hardware. General Terms Synthesis*

Hardware Synthesis of Explicit Model Predictive Controllers Autor Johansen, T.A., Jackson, W., Schreiber, R., Tondel, P.

“… in low-cost embedded control units. In this work, we report hardware synthesis results for this type of PWL control, and show that explicit MPC solutions can be implemented in an application…”
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Regularized level-set-based inverse lithography algorithm for IC mask synthesis Autor Geng, Zhen, Shi, Zheng, Yan, Xiao-lang, Luo, Kai-sheng

“…; that is, the topology of its result is usually too complicated to manufacture. We put forward a new algorithm with high pattern fidelity called regularized LSB-ILT implemented in partially coherent illumination （PCI…”
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Circuit Design for k-Coloring Problem and Its Implementation in Any Dimensional Quantum System Autor Saha, Amit, Saha, Debasri, Chakrabarti, Amlan

“…With the evolution of quantum computing, researchers nowadays tend to incline to find solutions to NP-complete problems using quantum algorithms to gain asymptotic advantage…”
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Tree-Based Hardware Recursion for Divide-And-Conquer Algorithms Autor Morrison, Braeden

“…It is well-known that custom hardware accelerators implemented as application-specific integrated circuits (ASICs…”
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The Efficiency of Convolution on Gemmini Deep Learning Hardware Accelerator Autor Gookyi, Dennis Agyemanh Nana, Wilson, Michael, Ahiadormey, Roger Kwao, Asiedu, Derek Kwaku Pobi, Danquah, Paul, Gyaang, Raymond

“… Recently, with the advancement of CMOS technology, the convolution operation in DL algorithms has been accelerated by being delegated to specialized hardware platforms such as Field Programmable Gate Array (FPGA) devices…”
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Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs Autor Plagwitz, Patrick, Streit, Franz-Josef, Becher, Andreas, Wildermann, Stefan, Teich, Jurgen

“…), still requires comprehensive hardware knowledge and sometimes long design cycles. Modern High-Level Synthesis (HLS…”
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A CAD System for Modeling and Simulation of Computer Networks Using Cellular Automata Autor Mardiris, V., Sirakoulis, G.Ch, Mizas, C., Karafyllidis, I., Thanailakis, A.

“… Algorithms for connectivity evaluation, system reliability evaluation, and shortest path computation in a computer network have also been implemented…”
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Scalable algorithm simplification using quantum AND logic Autor Chu, Ji, He, Xiaoyu, Zhou, Yuxuan, Yuan, Jiahao, Zhang, Libo, Guo, Qihao, Hai, Yongju, Han, Zhikun, Hu, Chang-Kang, Huang, Wenhui, Jia, Hao, Jiao, Dawei, Li, Sai, Liu, Yang, Ni, Zhongchu, Nie, Lifu, Pan, Xianchuang, Qiu, Jiawei, Wei, Weiwei, Nuerbolati, Wuerkaixi, Yang, Zusheng, Zhang, Jiajian, Zhang, Zhida, Zou, Wanjing, Chen, Yuanzhen, Deng, Xiaowei, Deng, Xiuhao, Hu, Ling, Li, Jian, Liu, Song, Lu, Yao, Niu, Jingjing, Tan, Dian, Xu, Yuan, Yan, Tongxing, Zhong, Youpeng, Yan, Fei, Sun, Xiaoming, Yu, Dapeng

“…Implementing quantum algorithms on realistic devices requires translating high-level global operations into sequences of hardware-native logic gates, a process known as quantum compiling…”
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An Exploration of FPGAs as Accelerators for Graph Analysis Via High-Level Synthesis Autor Silva, Pedro Filipe

“…) centres, making graph algorithms good candidates for hardware acceleration. Our work focuses on exploring FPGA acceleration of graph algorithms, following the HighLevel Synthesis (HLS) approach…”
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A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators Autor Ayupov, Andrey, Yesil, Serif, Ozdal, Muhammet Mustafa, Kim, Taemin, Burns, Steven, Ozturk, Ozcan

“… It has been shown that specialized hardware accelerators can achieve much better power and energy efficiency compared to the general purpose CPUs and GPUs…”
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SN-SEC: a secure wireless sensor platform with hardware cryptographic primitives Autor Moh’d, Abidalrahman, Aslam, Nauman, Phillips, William, Robertson, William, Marzi, Hosein

“… In this paper, we scrutinize the security holes in current WSNs platforms and compare the main approaches to implementing their cryptographic primitives in terms of security, time, and energy efficiency…”
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High-performance ECC processor architecture design for IoT security applications Autor Kudithi, Thirumalesu, Sakthivel, R.

“… The end nodes in IoT applications demand optimized device performance in terms of reduced power consumption and improved computing speed while not compromising on the security of the connected devices…”
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Method for designing specialized computing systems on the basis of hardware and software cooptimization Autor Tarasov, I. E., Sovietov, P. N., Lulyava, D. V., Duksin, N. A.

“… At the same time, balancing the pipeline stages during circuit synthesis at the register transfer level does not yet guarantee a balanced topological implementation of such a pipeline in terms…”
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AMP: Authentication of Media via Provenance Autor England, Paul, Malvar, Henrique S, Horvitz, Eric, Stokes, Jack W, Fournet, Cédric, Burke-Aguero, Rebecca, Chamayou, Amaury, Clebsch, Sylvan, Costa, Manuel, Deutscher, John, Erfani, Shabnam, Gaylor, Matt, Jenks, Andrew, Kane, Kevin, Redmiles, Elissa, Shamis, Alex, Sharma, Isha, Wenker, Sam, Zaman, Anika

“…Advances in graphics and machine learning have led to the general availability of easy-to-use tools for modifying and synthesizing media…”
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Virtual reconfigurable architecture for evolving combinational logic circuits Autor Wang, Jin, Lee, Chong-Ho

“…A virtual reconfigurable architecture (VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level…”
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Compilation, synthesis, and simulation of hardware description languages: The compositional models of HDL's Autor Cheng, Szu-Tsung

“…In this dissertation, we introduce a new hardware design language--V++. The heart of V++ is a new concept in hardware design languages…”
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Implementation of Neurobiological and Various Signal Processing Algorithms Using FPGA Circuits Autor Schäffer, László

“… FPGA.The dissertation consists of three major parts. The first chapter presents realtime detection and synthesis of neurophysiological signals based on FPGA, the second…”
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Testing DSP cores based on self-test programs Autor Zhao, W., Papachristou, C.

“…This paper presents a new method for the testing of the datapath of DSP cores based on self-test program. During the test, random patterns are loaded into the…”
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Tradeoff of FPGA Design of a Floating-point Library for Arithmetic Operators Autor Mu`ñoz, Daniel M., Sanchez, Diego F., Llanos, Carlos H., Ayala-Rincón, Mauricio

“… that must be computed in an efficient manner using a high precision and a large dynamic range. Commonly, these applications are implemented on personal computers taking advantage…”
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Team up: Cooperative memory management in embedded systems Autor Stilkerich, Isabella, Taffner, Philip, Erhardt, Christoph, Dietrich, Christian, Wawersich, Christian, Stilkerich, Michael

“…The use of a managed, type-safe languages such as Java in realtime and embedded systems can offer productivity and, in particular, safety and dependability…”
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