Search Results - algorithms implemented in hardware

The End of Moore's Law: A New Beginning for Information Technology by Theis, Thomas N., Wong, H.-S. Philip

“…The insights contained in Gordon Moore's now famous 1965 and 1975 papers have broadly guided the development of semiconductor electronics for over 50 years…”
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Dynamic Sparse Attention for Scalable Transformer Acceleration by Liu, Liu, Qu, Zheng, Chen, Zhaodong, Tu, Fengbin, Ding, Yufei, Xie, Yuan

“…Transformers are the mainstream of NLP applications and are becoming increasingly popular in other domains such as Computer Vision. Despite the improvements in…”
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Leveraging Modern C++ in High-Level Synthesis by Lahti, Sakari, Rintala, Matti, Hamalainen, Timo D.

“…High-level synthesis (HLS) enables the automated conversion of high-level language algorithms into synthesizable register-transfer level code, allowing computation-intensive algorithms to be accelerated on FPGAs…”
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A Fully-Pipelined Hardware Design for Gaussian Mixture Models by Conghui He, Haohuan Fu, Ce Guo, Luk, Wayne, Guangwen Yang

“… However, the parameters of a GMM need to be estimated from data by, for example, the Expectation-Maximization algorithm for Gaussian Mixture Models (EM-GMM…”
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Majority-Logic, its applications, and atomic-scale embodiments by Parhami, Behrooz, Abedi, Dariush, Jaberipur, Ghassem

“…Today's computing is increasingly data-intensive, heralding the age of big data. With greater data volumes, come the needs for faster processing, greater…”
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A New, Reconfigurable Circuit Offering Functionality of AND and OR Logic Gates for Use in Algorithms Implemented in Hardware by Talaska, Tomasz, Dlugosz, Rafal, Nikolic, Tatjana, Nikolic, Goran, Stefanski, Tomasz, Dlugosz, Michal, Talaska, Michal

“… There are many possible applications for this gate, mostly in artificial intelligence and pattern recognition algorithms implemented at the transistor level…”
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A hardware Gaussian noise generator using the Box-Muller method and its error analysis by Lee, D.-U., Villasenor, J.D., Luk, W., Leong, P.H.W.

“…We present a hardware Gaussian noise generator based on the Box-Muller method that provides highly accurate noise samples…”
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A Gaussian noise generator for hardware-based simulations by Lee, D.-U., Luk, W., Villasenor, J.D., Cheung, P.Y.K.

“…Hardware simulation offers the potential of improving code evaluation speed by orders of magnitude over workstation or PC-based simulation…”
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Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures by Shieh, Ming-Der, Lin, Wen-Ching

“…). This paper presents a new word-based Montgomery modular multiplication algorithm which can be used to achieve a low-latency scalable architecture for efficient hardware implementations…”
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Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations by Dong-U Lee, Cheung, R.C.C., Luk, W., Villasenor, J.D.

“…This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits…”
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Bounding Variable Values and Round-Off Effects Using Handelman Representations by Boland, D., Constantinides, G. A.

“…The precision used in an algorithm affects the error and performance of individual computations, the memory usage, and the potential parallelism for a fixed hardware budget…”
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FPGA-Based Real-Time Implementation of Detection Algorithm for Automatic Traffic Surveillance Sensor Network by Wójcikowski, Marek, Żaglewski, Robert, Pankiewicz, Bogdan

“…This paper describes the FPGA-based hardware implementation of an algorithm for an automatic traffic surveillance sensor network…”
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Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies by Jaberipur, Ghassem, Parhami, Behrooz, Abedi, Dariush

“…Petascale supercomputers are already pushing power boundaries that can be supplied or dissipated cost-effectively; greater challenges await us in the era of…”
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A new solution to the hyperbolic tangent implementation in hardware: polynomial modeling of the fractional exponential part by Nascimento, Ivo, Jardim, Ricardo, Morgado-Dias, Fernando

“…The most difficult part of an artificial neural network to implement in hardware is the nonlinear activation function…”
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An Ultra-Low Power, "Always-On" Camera Front-End for Posture Detection in Body Worn Cameras Using Restricted Boltzman Machines by Desai, Soham Jayesh, Shoaib, Mohammed, Raychowdhury, Arijit

“… This requires hardware assisted image recognition and template matching in the front-end, capable of making…”
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Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method by Cheung, R.C.C., Dong-U Lee, Luk, W., Villasenor, J.D.

“…We present an automated methodology for producing hardware-based random number generator (RNG…”
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Faulted phase selection multicriteria algorithm implemented in generic hardware for centralized P&C in smart grids by Villén Martínez, María Teresa, Comech, Maria Paz, Prada Hurtado, Anibal Antonio, Olivan, Miguel Angel, del Castillo, Carlos Rodriguez, Cortón, David López, Gallego, Rubén Andrino

“…•Digital substation.•Centralized protection and control (CPC).•Protection functions implemented in a generic hardware platform…”
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An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization by Jung Sub Kim, Lanping Deng, Mangalagiri, P., Irick, K., Sobti, K., Kandemir, M., Narayanan, V., Chakrabarti, C., Pitsianis, N., Xiaobai Sun

“…This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms…”
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FPGA-Based Virtual Screening Acceleration of Rigid-Molecule Docking by Navarro, Denis, Lucia, Oscar, Gil-Narvion, Jose M., Jimenez, Oscar

“…Virtual screening is a key process used to identify the most suitable molecule combinations when developing a new drug. Molecule docking is a commonly used…”
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High-Speed Algorithms and Architectures for Range Reduction Computation by Jaime, F J, Sánchez, M A, Hormigo, J, Villalba, J, Zapata, E L

“… This paper shows and compares a set of algorithms for additive range reduction computation and their corresponding application-specific integrated circuit implementations…”
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