Suchergebnisse - algorithms and (architectural OR architecture) for parallel processing
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An architectural framework for accelerating dynamic parallel algorithms on reconfigurable hardware
ISBN: 9781538662403, 153866240XVeröffentlicht: Piscataway, NJ, USA IEEE Press 20.10.2018Veröffentlicht in 2018 51st Annual IEEE ACM International Symposium on Microarchitecture (MICRO) (20.10.2018)“… In this paper, we propose ParallelXL, an architectural framework for building application-specific parallel accelerators with low manual effort …”
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A Fast CTU-level SAO Algorithm and Its Hardware Architecture for AVS3 Video Coding
ISSN: 2158-4001Veröffentlicht: IEEE 06.01.2024Veröffentlicht in Proceedings of IEEE International Symposium on Consumer Electronics (06.01.2024)“… To address this problem, a fast Coding Tree Unit (CTU)-level SAO algorithm and its hardware architecture is proposed …”
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Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design
ISSN: 2378-203XVeröffentlicht: IEEE 01.02.2020Veröffentlicht in Proceedings - International Symposium on High-Performance Computer Architecture (01.02.2020)“… In recent years, the CNNs have achieved great successes in the image processing tasks, e.g …”
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Implementing a Parallel Image Edge Detection Algorithm Based on the Otsu-Canny Operator on the Hadoop Platform
ISSN: 1687-5265, 1687-5273, 1687-5273Veröffentlicht: Cairo, Egypt Hindawi Publishing Corporation 01.01.2018Veröffentlicht in Computational intelligence and neuroscience (01.01.2018)“… parallel programming model that runs on the Hadoop platform. The Otsu algorithm is used to optimize the Canny …”
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Scalable Parallel Processing: Architectural Models, Real-Time Programming, and Performance Evaluation
ISSN: 2673-4591Veröffentlicht: MDPI AG 01.08.2025Veröffentlicht in Engineering proceedings (01.08.2025)“… This research paper analyzes and highlights the benefits of parallel processing to enhance performance and computational efficiency in modern computing systems …”
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Evaluation of parallel particle swarm optimization algorithms within the CUDA™ architecture
ISSN: 0020-0255, 1872-6291Veröffentlicht: Elsevier Inc 15.10.2011Veröffentlicht in Information sciences (15.10.2011)“… ), which are, in fact, massively parallel processing architectures. In this paper we discuss possible approaches to parallelizing PSO on graphics hardware within the Compute Unified Device Architecture (CUDA …”
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Resampling algorithms and architectures for distributed particle filters
ISSN: 1053-587X, 1941-0476Veröffentlicht: New York, NY IEEE 01.07.2005Veröffentlicht in IEEE transactions on signal processing (01.07.2005)“… In this paper, we propose novel resampling algorithms with architectures for efficient distributed implementation of particle filters …”
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Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems
ISSN: 1053-587X, 1941-0476Veröffentlicht: IEEE 01.04.2018Veröffentlicht in IEEE transactions on signal processing (01.04.2018)“… To address this problem, this paper proposes a preprocessing algorithm combining Cholesky sorted QR decomposition and partial iterative lattice reduction (CHOSLAR …”
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IOPA: I/O-aware parallelism adaption for parallel programs
ISSN: 1932-6203, 1932-6203Veröffentlicht: United States Public Library of Science 09.03.2017Veröffentlicht in PloS one (09.03.2017)“… With the development of multi-/many-core processors, applications need to be written as parallel programs to improve execution efficiency …”
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An Alpha-Tree Algorithm for Massively Parallel Architectures
ISSN: 1057-7149, 1941-0042, 1941-0042Veröffentlicht: United States IEEE 01.01.2025Veröffentlicht in IEEE transactions on image processing (01.01.2025)“… In this paper, we propose the first massively parallel alpha-tree algorithm that leverages concurrent union-find data structures to exploit the SIMT …”
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Accelerating Fourier and Number Theoretic Transforms using Tensor Cores and Warp Shuffles
Veröffentlicht: IEEE 01.09.2021Veröffentlicht in 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“… To speed things up, fast Fourier transform (FFT) algorithms, which are reduced-complexity formulations for computing the DFT of a sequence, have been proposed and implemented for traditional processors and their corresponding instruction sets …”
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An Efficient Implementation of the Bellman-Ford Algorithm for Kepler GPU Architectures
ISSN: 1045-9219, 1558-2183Veröffentlicht: New York IEEE 01.08.2016Veröffentlicht in IEEE transactions on parallel and distributed systems (01.08.2016)“… ) involves much more redundant work and a consequent waste of power consumption. This article presents a parallel implementation of the Bellman-Ford algorithm that exploits the architectural characteristics of recent GPU architectures (i.e …”
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STREAMINGGS: Voxel-Based Streaming 3D Gaussian Splatting with Memory Optimization and Architectural Support
Veröffentlicht: IEEE 22.06.2025Veröffentlicht in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“… We introduce STREAMINGGS, a fully streaming 3DGS algorithm-architecture co-design that achieves fine-grained pipelining and reduces DRAM traffic by transforming from a tile-centric rendering …”
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Parallel Branch-And-Bound Algorithms: Survey and Synthesis
ISSN: 0030-364X, 1526-5463Veröffentlicht: Linthicum, MD Operations Research Society of America 01.11.1994Veröffentlicht in Operations research (01.11.1994)“… We present a detailed and up-to-date survey of the literature on parallel branch-and-bound algorithms …”
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Parallel and accurate k‐means algorithm on CPU‐GPU architectures for spectral clustering
ISSN: 1532-0626, 1532-0634Veröffentlicht: Hoboken Wiley Subscription Services, Inc 25.06.2022Veröffentlicht in Concurrency and computation (25.06.2022)“… We propose parallel optimization techniques for the k‐means algorithm on CPU and GPU. Particularly we use a two …”
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An efficient heterogeneous parallel password recovery system on MT-3000
ISSN: 0920-8542, 1573-0484Veröffentlicht: New York Springer US 01.01.2025Veröffentlicht in The Journal of supercomputing (01.01.2025)“… However, as encryption algorithms and complex passwords become more prevalent for security purposes, traditional CPU-based and GPU-based password recovery systems are struggling to meet the time …”
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Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture
ISSN: 1549-7747, 1558-3791Veröffentlicht: New York IEEE 01.08.2021Veröffentlicht in IEEE transactions on circuits and systems. II, Express briefs (01.08.2021)“… ) segregation technique. Subsequently, we present hardware-efficient QC-LDPC decoder-architecture based on the proposed algorithm and additional architectural optimizations …”
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An efficient hardware supported and parallelization architecture for intelligent systems to overcome speculative overheads
ISSN: 0884-8173, 1098-111XVeröffentlicht: New York John Wiley & Sons, Inc 01.12.2022Veröffentlicht in International journal of intelligent systems (01.12.2022)“… time‐consuming and central processing unit intensive. As a consequence, parallel processing systems are gaining popularity to enhance overall computer performance …”
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Auto-GNAS: A Parallel Graph Neural Architecture Search Framework
ISSN: 1045-9219, 1558-2183Veröffentlicht: New York IEEE 01.11.2022Veröffentlicht in IEEE transactions on parallel and distributed systems (01.11.2022)“… Graph neural architecture search effectively constructs the GNNs that achieve the expected model performance with the rise of automatic machine learning …”
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Max-PIM: Fast and Efficient Max/Min Searching in DRAM
Veröffentlicht: IEEE 05.12.2021Veröffentlicht in 2021 58th ACM/IEEE Design Automation Conference (DAC) (05.12.2021)“… In this work, for the first time, we propose a novel 'Min/Max-in-memory' algorithm based on iterative XNOR bit-wise comparison, which supports parallel inmemory searching for minimum and maximum …”
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