Suchergebnisse - algorithms AND architecture for parallel processing

ICAPP 95 : IEEE First ICA[3]PP : IEEE First International Conference on Algorithms and Architectures for Parallel Processing, Brisbane, Australia, 19-21 April, 1995 von IEEE International Conference on Algorithms and Architectures for Parallel Processing, Narasimhan, V. L.

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Proceedings fifth International Conference on algorithms and architectures for parallel processing von IEEE International Conference on Algorithms and Architectures for Parallel Processing, Zhou, Wanlei

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Call for Papers: Advances in Parallel Graph Processing: Algorithms, Architectures, and Application Frameworks

“… Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers …”
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Call for Papers: Advances in Parallel Graph Processing: Algorithms, Architectures, and Application Frameworks House Advertisement

“… Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers …”
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Guest Editorial: Advances in Parallel Graph Processing: Algorithms, Architectures, and Application Frameworks von Kalyanaraman, Ananth, Halappanavar, Mahantesh

“… The papers in this special section explore recent advancements in parallel graph processing …”
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Special issue: International conference on algorithms and architectures for parallel processing (ICA3PP'09): Foreword von Horng, Shi-Jinn

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Proceedings of 1996 IEEE Second International Conference on Algorithms & Architectures for Parallel Processing, ICA[3]PP '96, June 11-13, 1996, Singapore von IEEE International Conference on Algorithms and Architectures for Parallel Processing, Institute of Electrical and Electronics Engineers. Singapore Section, IEEE Singapore Section. Computer Chapter, National University of Singapore. Dept. of Information Systems and Computer Science

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Algorithms and architectures for parallel processing: 1997 3rd international conference, Melbourne, Australia, December 10-12 1997 von Goscinski, Andrzej, Zhou, Wanlei, Hobbs, Michael

“… This volume of proceedings describes the lower costs and higher degrees of integration of chip architecture which allow parallel processing …”
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Comparison of Semi-Implicit and Explicit Finite Difference Algorithms on Highly Parallel Processing Architectures von Kirkpatrick, Michael P., Armfield, Steven W., Stewart, Nicholas J., Lin, Wen Xian, Holmes, David W.

“… Their performance derives from the highly parallel architecture that is em-ployed and have the benefit of low cost, temperature and power consumption …”
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An Alpha-Tree Algorithm for Massively Parallel Architectures von Carlinet, Edwin, Kaci, Quentin, Blin, Nicolas

“… In this paper, we propose the first massively parallel alpha-tree algorithm that leverages concurrent union-find data structures to exploit the SIMT …”
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Algorithms to Speed Up Contour Tracing in Real Time Image Processing Systems von Gupta, Sonal, Kar, Subrat

“… As single processor architectures reach their performance limits, parallel processing architectures offer energy efficient and high performance solutions for real time applications …”
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Parallel Processor Architecture with a New Algorithm for Simultaneous Processing of MIPS-Based Series Instructions von Hadizadeh, Ali, Tanghatari, Ehsan

“… In this paper, new architecture based on this processor, with new parallel processing design, is provided to allow parallel execution of instructions dynamically …”
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Real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors von Klilou, Abdessamad, Bourzeix, Francois, Bourja, Omar, Zennayi, Yahya, Mabrouk, Lhoussein, Belkouch, Said

“… Machine vision algorithms require high-computing power. A high performance parallel system has been proposed in this paper by implementing a road traffic radar video processing chain in real-time on a new embedded architecture …”
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Algorithms And Architectures For Parallel Processing - Proceedings Of The 1997 3rd International Conference von Goscinski, Andrzej Marian, Zhou, Wan Lei, Hobbs, Michael

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Design and VLSI Implementation of Multilayered Neural Network Architecture Using Parallel Processing and Pipelining Algorithm for Image Compression von Mohan, Murali, ., Sathyanarayana

“… In this paper, an optimized high speed parallel processing architecture with pipelining for multilayer neural network for image compression and decompression is implemented on FPGA …”
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1997 3rd International Conference on Algorithms & Architectures for Parallel Processing, ICA[3]PP '97, Melbourne, Australia Decsmber 10-12 1997 von IEEE International Conference on Algorithms and Architectures for Parallel Processing, Institute of Electrical and Electronics Engineers. Victorian section, Gościński, Andrzej, Hobbs, Michael, Zhou, Wanlei, Deakin University Faculty of Science and Technology, Deakin University IEEE Victorian Section

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Mapping High-Fidelity Volume Rendering for Medical Imaging to CPU, GPU and Many-Core Architectures von Smelyanskiy, M., Holmes, D., Chhugani, J., Larson, A., Carmean, D.M., Hanson, D., Dubey, P., Augustine, K., Kim, D., Kyker, A., Lee, V.W., Nguyen, A.D., Seiler, L., Robb, R.

“… We motivate and analyze new volumetric rendering algorithms that are suited to modern parallel processing architectures …”
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GPU-Oriented Parallel Algorithm for Histogram Statistical Image Enhancement von XIAO Han, SUN Lupeng, LI Cailin, ZHOU Qinglei

“… the expected satisfactory speed. In view of this deficiency, this paper realizes the parallel processing of histogram statistical image enhancement algorithm on graphics processing unit (GPU …”
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A radix sorting parallel algorithm suitable for graphic processing unit computing von Xiao, Shi‐yang, Li, Cai‐lin, Guo, Bao‐yun, Xiao, Han

“… Summary Radix sorting is an essential basic data processing operation in many computer fields …”
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Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning von Soleimani, Parastoo, Capson, David W., Li, Kin Fun

“… The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2 …”
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