Search Results - algorithm hardware implementation
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Minimum-clock-cycle Itoh-Tsujii algorithm hardware implementation for cryptography applications over GF (2 m ) fields
ISSN: 0013-5194, 1350-911XPublished: Stevenage Institution of Engineering and Technology 30.08.2012Published in Electronics letters (30.08.2012)Get full text
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A Hardware Implementation of Spaceborne SAR BP Algorithm Based on Precise Region Focusing and Hardware-Software Collaboration
ISSN: 1939-1404, 2151-1535Published: Piscataway IEEE 2025Published in IEEE journal of selected topics in applied earth observations and remote sensing (2025)“… Given the limited resources of the satellite's hardware platform, the traditional hardware implementation of the algorithm…”
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"MR Q-Learning" Algorithm for Efficient Hardware Implementations
ISSN: 2576-2303Published: IEEE 31.10.2021Published in Conference record - Asilomar Conference on Signals, Systems, & Computers (31.10.2021)“…The maximum value finder block is one of the most critical parts in the hardware implementation of the Q-Learning Reinforcement Learning algorithm…”
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Conference Proceeding -
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Security of Block Ciphers: From Algorithm Design to Hardware Implementation
ISBN: 9781118660010, 1118660013, 1118660048, 9781118660041Published: Singapore Wiley 2015“… * Unique in its combination of both algorithmic-level design and hardware-level implementation…”
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Area–Time-Efficient High-Radix Modular Inversion Algorithm and Hardware Implementation for ECC over Prime Fields
ISSN: 2073-431X, 2073-431XPublished: Basel MDPI AG 01.10.2024Published in Computers (Basel) (01.10.2024)“… We investigate the state-of-the-art modular inversion algorithms, and evaluate the performance and cost of the algorithms and their hardware implementations…”
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Minimum-clock-cycle Itoh-Tsujii algorithm hardware implementation for cryptography applications over GF(2^sup m^) fields
ISSN: 0013-5194, 1350-911XPublished: Stevenage John Wiley & Sons, Inc 30.08.2012Published in Electronics letters (30.08.2012)“… The Itoh-Tsujii algorithm (ITA) provides high performance implementations for the inversion operation in standard bases through diverse versions like squarer-ITA, parallel squarer-ITA or quad-ITA…”
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Journal Article -
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Direct Neural-Network Hardware-Implementation Algorithm
ISSN: 0278-0046, 1557-9948Published: New York IEEE 01.05.2010Published in IEEE transactions on industrial electronics (1982) (01.05.2010)“…An algorithm for compact neural-network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function…”
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A Ultra-Low Cost and Accurate AMC Algorithm and Its Hardware Implementation
ISSN: 2644-1268, 2644-1268Published: IEEE 01.01.2025Published in IEEE open journal of the Computer Society (01.01.2025)“… To address the challenges of speed and accuracy, this article presents a low-cost, and accurate AMC algorithm and its FPGA implementation that can achieve both fast and accurate results at the same time…”
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Real-time optical flow processing on embedded GPU: an hardware-aware algorithm to implementation strategy
ISSN: 1861-8200, 1861-8219Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.04.2022Published in Journal of real-time image processing (01.04.2022)“… For achieving this processing in real time, the whole algorithm deployment chain must be thought of for efficiency first…”
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Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON‐Galois/Counter Mode
ISSN: 0098-9886, 1097-007XPublished: Bognor Regis Wiley Subscription Services, Inc 01.12.2023Published in International journal of circuit theory and applications (01.12.2023)“…Summary This brief proposes a new lightweight authenticated encryption algorithm SIMON…”
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A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm
ISSN: 0098-9886, 1097-007XPublished: Bognor Regis Wiley Subscription Services, Inc 01.12.2023Published in International journal of circuit theory and applications (01.12.2023)“…In this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process…”
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Computer vision algorithms and hardware implementations: A survey
ISSN: 0167-9260, 1872-7522Published: Amsterdam Elsevier B.V 01.11.2019Published in Integration (Amsterdam) (01.11.2019)“… This paper aims at providing a comprehensive survey of the recent progress on computer vision algorithms and their corresponding hardware implementations…”
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Optimization and hardware implementation of noise reduction algorithm for low‐power audio chip
ISSN: 1532-0626, 1532-0634Published: 20.01.2022Published in Concurrency and computation (20.01.2022)“…‐power hardware implementation are studied. Several types of common noise reduction algorithms are analyzed and simulated, and the log…”
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Algorithm and hardware implementation for visual perception system in autonomous vehicle: A survey
ISSN: 0167-9260, 1872-7522Published: Amsterdam Elsevier B.V 01.09.2017Published in Integration (Amsterdam) (01.09.2017)“…This paper briefly surveys the recent progress on visual perception algorithms and their corresponding hardware implementations for the emerging application of autonomous driving…”
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Local tone mapping algorithm and hardware implementation
ISSN: 0013-5194, 1350-911X, 1350-911XPublished: The Institution of Engineering and Technology 03.05.2018Published in Electronics letters (03.05.2018)“…A novel tone mapping algorithm and hardware implementation for displaying wide dynamic range (WDR…”
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Decoder-Side Motion Vector Refinement in VVC: Algorithm and Hardware Implementation Considerations
ISSN: 1051-8215, 1558-2205Published: New York IEEE 01.08.2021Published in IEEE transactions on circuits and systems for video technology (01.08.2021)“… Furthermore, the hardware implementation considerations of the DMVR design are particularly focused in this study…”
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An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC
ISSN: 1063-8210, 1557-9999Published: New York IEEE 01.02.2025Published in IEEE transactions on very large scale integration (VLSI) systems (01.02.2025)“… In this context, this article proposes an interpolation-free algorithm based on an error surface to improve the throughput of FME hardware…”
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Initial settings of Berlekamp‐Massey algorithm for efficient hardware implementation
ISSN: 1350-911X, 0013-5194, 1350-911XPublished: Stevenage The Institution of Engineering and Technology 31.01.2013Published in Electronics letters (31.01.2013)“…‐based algorithms and architectures have been presented in recent years. Introduced are different initial settings of the BM algorithm that can reduce cost and power consumption for VLSI implementation…”
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Soft decoding of the (23, 12, 7) Golay code: simplified algorithm and hardware implementation
ISSN: 1751-8628, 1751-8636Published: Stevenage John Wiley & Sons, Inc 18.12.2012Published in IET communications (18.12.2012)“… Based on the simplified algorithm, this study investigates an efficient hardware implementation on field programmer gate array platform, and presents a detailed architecture of the soft decoder. Experimental result indicates that, the proposed algorithm uses less hardware complexity and has high-throughput rate, therefore it is naturally suitable for very large scale integration implementation…”
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A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation
ISSN: 1051-8215, 1558-2205Published: New York IEEE 01.08.2018Published in IEEE transactions on circuits and systems for video technology (01.08.2018)“… In response to this challenge, we developed a hardware-oriented integer ME algorithm and the related hardware implementation…”
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