Search Results - VLSI-array processor architecture

A VLSI Array Processor Architecture for Emulating Resistive Network Filtering by Kananen, Asko

“…This thesis deals with silicon implementations of an all-transistor analogue parallel processor that emulates the functionality of a resistive network…”
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Architecture and simulation of selected fine-grained VLSI array processors by Wu, Tony Hung-Yao

“… Scalability and massive parallelism provide the enormous throughput rate and processing capability that conventional sequential processors cannot achieve…”
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A complete system for NN classification based on a VLSI array processor by Ferrari, A., Borgatti, M., Guerrieri, R.

“…This paper describes a VLSI array processor system designed and built for classification problems based on the k-nearest-neighbors approach…”
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An improved algorithm for accelerating reconfiguration of VLSI array by Qian, Junyan, Mo, Fuhao, Ding, Hao, Zhou, Zhide, Zhao, Lingzhong, Zhai, Zhongyi

“… In this paper, we describe a new method to speed up the reconfiguration for the VLSI arrays. An efficient algorithm was proposed based on shortest path first principle…”
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Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect by Ding, Hao, He, Yanlong, Zhai, Zhongyi, Li, Zhi, Qian, Junyan, Zhao, Lingzhong

“…With the progressive augmentation of the density of 3-D processor arrays, some processor elements (PEs…”
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Basic hardware module for a nonlinear programming algorithm and applications by Lin, Shin-Yeu

“…We present a VLSI-array-processor architecture for the implementation of a nonlinear programming algorithm that solves discrete-time optimal control problems for nonlinear systems with control constraints…”
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A compact real-time vision system using integrated memory array processor architecture: VLSI for video signal processing by OKAZAKI, S, FUJITA, Y, YAMASHITA, N

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A VLSI array architecture for realization of DFT, DHT, DCT and DST by Maharatna, K., Dhar, A.S., Banerjee, Swapna

“…A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC…”
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Design of fine grain VLSI array processor for real-time 2D digital filtering by Iwata, Y., Kawamata, M., Higuchi, T.

“… The architecture of the VLSI array processors is a linear systolic array, of which processing elements (PEs…”
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VLSI array algorithms and architectures for RSA modular multiplication by Yong-Jin Jeong, Burleson, W.P.

“…We present two novel iterative algorithms and their array structures for integer modular multiplication. The algorithms are designed for Rivest-Shamir-Adelman…”
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VLSI Array processors by Kung, S.

“…High speed signal processing depends critically on parallel processor technology…”
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An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray by Qian, Junyan, Huang, Bisheng, Ding, Hao, Zhou, Zhide, Zhao, Lingzhong, Zhai, Zhongyi

“…Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs…”
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New VLSI array processor design for image window operations by Li, D.J., Jiang, L., Isshiki, T., Kunieda, H.

“…A novel architecture named window-memory sharing processor array is proposed, which targets window operations in image processing…”
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Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing by Lopich, A., Dudek, P.

“…This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discrete- and continuous-time domains…”
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A VLSI array processor accelerator for k-NN classification by Ferrari, A., Borgatti, M., Guerrieri, R.

“…This paper describes a VLSI array processor system that has been designed and built for classification problems based on the k-nearest neighbors approach…”
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Online CORDIC algorithm and VLSI architecture for implementing QR-array processors by Hamill, R., McCanny, J.V., Walke, R.L.

“…A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition…”
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CAPE-VLSI implementation of a systolic processor array: architecture, design and testing by Hemkumar, N.D., Kota, K., Cavallaro, J.R.

“… However, the SVD is computationally intensive. The CORDIC array processor element (CAPE) is a single chip VLSI implementation of a processor element for the Brent-Luk-VanLoan systolic array which computes the SVD of a real matrix…”
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Scalable linear array architectures for matrix inversion using Bi-z CORDIC by Luo, J.W., Jong, C.C.

“…In this paper, VLSI array architectures for matrix inversion are studied. A new binary-coded z-path (Bi-z…”
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Area time trade-offs in micro-grain VLSI array architectures by Singh Bajwa, R., Owens, R.M., Irwin, M.J.

“… The processor architectures being considered are: an associative memory architecture, a Mux-based SIMD architecture and a modification of the Mux-based architecture using RAMs making it suitable for systolic MIMD/MISD computation…”
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Multilevel simulation tool for designing fault-tolerant VLSI array processors by Poechmueller, P., Sharma, G.K., Glesner, M.

“… The array specification language of this tool allows VLSI designer to specify the input at dependence graph, signal flow graph and processor architecture-level…”
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